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My Biography

Until July 2009 I was a design engineer / industrial researcher with over 18 years of diverse experience in microelectronics and communication systems. I concentrated on large system-on-chip (SoC) designs for wireless applications but my prior involvement also included analog, RF, mixed-signal and digital designs. I have also acquired communication systems analysis skills and was engaged in software development. I have been a team leader who works well and communicates effectively with system, software, as well as analog and digital circuit design teams. My strengths lie in deep analytical skills that lead to novel solutions that offer clear advantages over existing designs. I am always striving to find most optimal solutions not only from the circuit design perspective, but also business, process technology, system and architecture. This commitment to innovation, quality and attention to detail has resulted in tens of full-custom mixed-signal complex IC chips, all 1st pass successes. I have been elevated to an IEEE Fellow for contributions to the digital RF communications systems. In 2012, I won a prestigious IEEE Circuits and Systems Industrial Pioneer Award.

I left industry for academia in July 2009, joining Delft University of Technology (TU Delft) in the Netherlands. In Sept. 2014 I joined University College Dublin (UCD) in Ireland as full-time (Full) Professor while still holding a part-time (Full) Professor position at TU Delft. I have co-authored three books, six book chapters, 170 journal and conference publications, and hold 140 issued US patents.

PROFESSIONAL EXPERIENCE

University College Dublin (UCD), Dublin, Ireland, since September 2014. Position: (Full) Professor in School of Electrical, Electronic & Communications Engineering. Carrying out research and teaching in the area of microelectronic circuit design; concentrating in frequency synthesis and RF using advanced CMOS for Internet-of-Things (IoT).

Currently, I supervise 4 postdocs, 17 PhDs, 2 visting-PhDs.

IoE2lab

Delft University of Technology (TU Delft), Delft, the Netherlands. July 2009 to present. Carrying out research and teaching in the area of microelectronics, concentrating in frequency synthesis and RF using advanced CMOS.

Currently, I supervise 5 PhDs.

Digital RF Processor (DRP™) Group, Texas Instruments (TI), Dallas, Texas Sept. 1999 – June 2009. Invented, developed and popularized the Digital RF Processor (DRP) technology: A novel all-digital frequency synthesizer, all-digital RF transmitter and discrete-time RF receiver architecture that is suitable for the mainstream digital CMOS processes and presents a unique opportunity to build ultra low-cost and power-efficient single-chip radios. The DRP architecture was designed from the ground up for the nanoscale CMOS with its inherent limitations of low voltage headroom, analog-unfriendly transistors, large substrate noise from the digital baseband, MOS device modeling and process variability. Pioneered the use of scaled CMOS for RF application at the time when SiGe technology was considered unquestionably superior. This research has resulted in 80 issued US patents, as well as 120 journal and conference publications. TI's BRF6150 Bluetooth IC, the first generation of DRP, and the second generation of DRP for the single-chip GSM cellular phones (“Locosto” and “UPPcosto”) are in high volume production. Between 2007 to 2009, I was a CTO of the DRP group engaged in strategic research. Holder of an elected title of Distinguished Member of Technical Staff (limited to 2% of all TI engineers). Elected to IEEE Fellow title (class of 2009) for the work on digitalization of RF.

Hard Disk Drive Read Channel Group, Texas Instruments (TI), Dallas, Texas Aug. 1995 – Sept. 1999. Developed a new digitally-intensive CMOS read channel architecture for magnetic recording hard-disk drives. Developed a top-down VHDL methodology and simulation/modeling environment for the mixed-signal system-on-chip (SoC) IC Designed ultra-high-speed (550 MHz) 8-tap 6-bit FIR filter and LMS coefficient adaptation, phase detector, timing and gain error correction circuits in 0.18 um CMOS. Designed sync detect circuit and LMS adaptation in 0.5 um BiCMOS. Resulted in 12 issued US patents and 11 journal and conference publications.

Alcatel Network Systems, Richardson, Texas, USA May 1991 – Aug. 1995. Design work in telecommunications systems, discrete analog and digital circuits, high-speed signal integrity, software algorithms. Gained complete expertise of an entire clock subsystem of a large telecommunications SONET cross-connect system. Granted two US patents.

EDUCATION

Ph.D. in Electrical Engineering, University of Texas at Dallas, USA. Thesis “Digital deep-submicron CMOS frequency synthesis for RF wireless applications,” July 2002. M.S. in Electrical Engineering, University of Texas at Dallas, USA, with concentration in digital systems, Dec. 1992. B.S. in Electrical Engineering, Summa Cum Laude, University of Texas at Dallas, USA, with concentration in telecommunications, May 1991.

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