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2023

[1] K. Xu, B. Yu, J. Hu, Y. Li, R. B. Staszewski, F. Lin and H. Xu, “A 50µW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 15 June 2023, sec. C26-4, pp. 1–2, Kyoto, Japan. DOI: 10.23919/VLSITechnologyandCir57934.2023.10185366. [IEEE Xplore link]

[2] W. Tao, W. Zhao, R. B. Staszewski, F. Lin and Y. Hu, “An 18.8–to–23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and –252 dB FoM,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 14 June 2023, sec. C13-3, pp. 1–2, Kyoto, Japan. DOI: 10.23919/VLSITechnologyandCir57934.2023.10185415. [IEEE Xplore link]

[3] Z. Ren, T. Siriburanon and R. B. Staszewski, “Rapid Locking Range Analysis of a Sub-Harmonic ILO considering Injection Waveforms of Different Multiplied Ratios,” Proc. of 34 Irish Signals and Systems Conf. (ISSC), 13–14 Jun. 2023, pp. 1–4, Dublin, Ireland. DOI: 10.1109/ISSC59246.2023.10162067. [IEEE Xplore link]

[4] C. Lambkin, V. Nguyen and R. B. Staszewski, “A Neural-Recording 0.2-V VCO-based ADC with Machine-Learning-Programmable Coupled Oscillator Ensembles,” Proc. of 34 Irish Signals and Systems Conf. (ISSC), 13–14 Jun. 2023, pp. 1–6, Dublin, Ireland. DOI: 10.1109/ISSC59246.2023.10162043. [IEEE Xplore link]

[5] E. Alarcon, S. Abadal, F. Sebastiano, M Babaie, E. Charbon, P. Haring Bolivar, M. Palesi, E. Blokhina, D. Leipold, B. Staszewski, A Garcia-Saez and C. Almudever, “Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package,” Proc. of IEEE Intl. Symp. on Circuits and Systems (ISCAS), paper 2330, sec. xx-x, pp. 1–5, 23 May 2023, Monterey, CA, USA. DOI: 10.1109/ISCAS46773.2023.10181857. [IEEE Xplore link]

[6] L. Fanals, E. Alarcon, I. Bashir, E. Blokhina, D. Leipold and R. B. Staszewski, “Tunable LC resonator for multiplexed multi-qubit readout,” Proc. of IEEE Intl. Symp. on Circuits and Systems (ISCAS), paper 2297, sec. x-x, pp. 1–5, 23 May 2023, Monterey, CA, USA. DOI: 10.1109/ISCAS46773.2023.10182075. [IEEE Xplore link]

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2022

[1] C. Power, D. Andrade-Miceli, I. Bashir, M. Asker, D. Leipold, R. B. Staszewski and E. Blokhina, “Modelling of Electron Injec- tion and Confinement in Cryogenic 22-nm FD-SOI Quantum Dot Arrays,” Proc. of 29th IEEE International Conf. on Electronics Circuits and Systems (ICECS), 26 Oct. 2022, pp. 1–4, Glasgow, UK.

[2] D. Andrade-Miceli, C. Power, A. Esmailiyan, T. Siriburanon, I. Bashir, M. Asker, D. Leipold, R. B. Staszewski and E. Blokhina, “Characterisation and Modelling of 22-nm FD-SOI Transistors Operating at Cryogenic Temperatures,” Proc. of 29th IEEE Inter- national Conf. on Electronics Circuits and Systems (ICECS), 26 Oct. 2022, pp. 1–4, Glasgow, UK.

[3] X. Wu, P. Giounanlis, E. Blokhina and R. B. Staszewski, “Control of Quantum Systems: Comparison of Different Techniques by the Example of Charge and Spin Semiconductor Qubits,” Proc. of 29th IEEE International Conf. on Electronics Circuits and Systems (ICECS), 26 Oct. 2022, pp. 1–4, Glasgow, UK.

[4] C. Power, R. B. Staszewski and E. Blokhina, “Cryogenic Transistor Confinement Well Simulation Through Material and Carrier Transport Decoupling,” Proc. of 29th IEEE International Conf. on Electronics Circuits and Systems (ICECS), 25 Oct. 2022, poster 35, pp. 1–2, Glasgow, UK. (“Best Poster Award”)

[5] A. Bozorg, S. Gruszczynski and B. Staszewski, “An 85-GHz Low-Power Low-Noise Amplifier with 15 GHz Bandwidth in 22nm FD-SOI CMOS for 5G Communications,” Proc. of IEEE 24th International Microwave and Radar Conf. (MIKON), sec. MO7-3, pp. 1–3, 12 Sept. 2022, Gdansk, Poland. [IEEE Xplore link]

[6] X. Chen, T. Siriburanon, A. Zhu and R. B. Staszewski, “A Digital-to-Time Converter Based on Crystal Oscillator Waveform Achieving 86-fs Jitter in 22-nm FD-SOI CMOS,” Proc. of IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RTu4B.3, pp. 215–218, 21 Jun. 2022, Denver, CO, USA. DOI: 10.1109/RFIC54546.2022.9863080. [IEEE Xplore link]

[7] Z. Gao, M. Fritz, J. He, G. Spalink, R. B. Staszewski, M. Alavi and M. Babaie, “A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 14 June 2022, sec. C01-4, pp. 1–2, Honolulu, HI, USA. DOI: 10.1109/VLSITechnologyand Cir46769.2022.9830398. [IEEE Xplore link]

[8] T.-H. Tsai, R.-B. Sheen, S.-Y. Hsu, Y.-T. Chang, C.-H. Chang and R. B. Staszewski, “A cascaded PLL (LC-PLL + RO- PLL) with a programmable double realignment achieving 204fs integrated jitter (100kHz to 100MHz) and -72dB reference spur,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), 23 Feb. 2022, pp. xx–xx, sec. 23.1, San Francisco, CA, USA. DOI: 10.1109/ISSCC42614.2022.9731676. [IEEE Xplore link]

[9] Z. Gao, J. He, M. Fritz, J. Gong, Y. Shen, Z. Zong, P. Chen. G. Spalink, B. Eitel, K. Yamamoto, R. B. Staszewski, M. Alavi and M. Babaie, “A 2.6-to-4.1GHz fractional-N digital PLL based on a time-mode arithmetic unit achieving -249.4dB FoM and -59dBc fractional spurs,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), 23 Feb. 2022, pp. xx–xx, sec. 23.3, San Francisco, CA, USA. DOI: 10.1109/ISSCC42614.2022.9731561. [IEEE Xplore link]

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2021

[1] P. Chen, X. Meng, J. Yin, P.-I. Mak, R. P. Martins and R. B. Staszewski, “A 529–µW fractional–N all–digital PLL using TDC gain auto–calibration and an inverse–class–F DCO in 65–nm CMOS”, IEEE International Symposium on Integrated Circuits and Systems (ISICAS), 10 Dec. 2021, pp.xx–xx, sec. 3A-3, ID. 246, Singapore. (TCAS-I) DOI: 10.1109/TCSI.2021.3094094. [IEEE Xplore link (Open Access)]

[2] H. Ghaedrahmati, J. Zhou and R. B. Staszewski, “A 38.6-fJ/conv.-step inverter-based continuous-time bandpass ΔΣ ADC in 28 nm using asynchronous SAR quantizer”, IEEE International Symposium on Integrated Circuits and Systems (ISICAS), 10 Dec. 2021, pp. xx–xx, sec. 3B-2, ID. 9599, Singapore. (TCAS-II) DOI: 10.1109/TCSII.2021.3089831. [IEEE Xplore link (Open Access)]

[3] P. Chen, J. Yin, F. Zhang, P.-I. Mak, R. P. Martins and R. B. Staszewski, “Mismatch analysis of DTCs with an improved BIST- TDC in 28-nm CMOS”, IEEE International Symposium on Integrated Circuits and Systems (ISICAS), 11 Dec. 2021, pp.xx–xx, sec. 4C-1, ID. 455, Singapore. (TCAS-I) DOI: 10.1109/TCSI.2021.3105451. [IEEE Xplore link (Open Access)]

[4] G. R. Nikandish, A. Nasri, A. Yousefi, A. Zhu and R. B. Staszewski, “A broadband fully integrated power amplifier using waveform shaping multi-resonance harmonic matching network,” IEEE International Symposium on Integrated Circuits and Systems (ISICAS), 11 Dec. 2021, pp.xx–xx, sec. 4B-2, ID. 341, Singapore. (TCAS-I) DOI: 10.1109/TCSI.2021.3095708. [IEEE Xplore link (Open Access)]

[5] A. Bozorg and R. B. Staszewski, “A 20 MHz–2 GHz inductorless two-fold noise-canceling low-noise amplifier in 28-nm CMOS”, IEEE International Symposium on Integrated Circuits and Systems (ISICAS), 11 Dec. 2021, pp.xx–xx, sec. 4C-3, ID. 253, Singapore. (TCAS-I) DOI: 10.1109/TCSI.2021.3092960. [IEEE Xplore link (Open Access)]

[6] E. Kobal, T. Siriburanon, R. B. Staszewski and A. Zhu, “A 28 GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22 nm FD-SOI CMOS,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. B4L-6, pp.377–380, 16 Sept 2021, Grenoble, France(remote). DOI: 10.1109/ESSCIRC53450.2021.9567845. [IEEE Xplore link]

[7] A. Bozorg and R. B. Staszewski, “A charge-rotating IIR filter with linear interpolation and high stop-band rejection,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. B2L-6, pp.335–338, 16 Sept. 2021, Grenoble, France (remote). DOI:10.1109/ESSCIRC53450.2021.9567811. [IEEE Xplore link]

[8] I. Bashir, D. Leipold, M. Asker, A. Esmailiyan, E. Blokhina, D. Redmond, P. Giounanlis, D. Andrade-Miceli and R. B. Staszewski, “Bias Generation and Calibration of CMOS Charge Qubits at 3.5 Kelvin in 22-nm FDSOI,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. A5L-6, pp.47–50, 14 Sept. 2021, Grenoble, France (remote). DOI: 10.1109/ES- SCIRC53450.2021.9567784. [IEEE Xplore link]

[9] P. Chen, F. Zhang, S. Hu and R. B. Staszewski, “A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤0.12% INL/Range over >100mV Supply Range” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 18 June 2021, sec. C17-4, pp. 1–2, Kyoto, Japan (remote ). DOI: 10.23919/VLSICircuits52068.2021.9492452. [IEEE Xplore link]

[10] J. Du, T. Siriburanon, X. Chan, Y. Hu, V. Govindaraj, A. Zhu and R. B. Staszewski, “A 24–31 GHz Reference Oversampling ADPLL Achieving FoMjitter-Nof -269.3 dB,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 18 June 2021, sec. C17-2, pp. 1–2, Kyoto, Japan (remote ). DOI: 10.23919/VLSICircuits52068.2021.9492340. [IEEE Xplore link]

[11] H. M. Nguyen, J. S. Walling, A. Zhu and R. B. Staszewski, “A Ka-band Switched-Capacitor RFDAC Using Edge-Combining in 22nm FD-SOI,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 17 June 2021, sec. C12-2, pp. 1–2, Kyoto, Japan (remote). DOI:10.23919/VLSICircuits52068.2021.9492451. [IEEE Xplore link]

[12] D. Andrade-Miceli, A. Esmailiyan, P. Bisiaux, E. Blokhina, T. Siriburanon, I. Bashir, M. Asker, D. Leipold and R. B. Staszewski, “Cryogenic Low-Drop-Out Regulators Fully Integrated with Quantum Dot Array in 22-nm FD-SOI CMOS,” Proc. of IEEE International Microwave Symp. (IMS), sec. WeIF1, ID 310-HL970, pp.1–3, 7-10 June. 2021, Atlanta, GA, USA.(remote). DOI:10.1109/IMS19712.2021.9574910. [IEEE Xplore link]

[13] E. Kobal, M. Usman, T. Siriburanon, R. B. Staszewski and A. Zhu, “A Low Profile Highly Isolated Phased Array MIMO Antenna System for 5G Applications at 28 GHz,” Proc. of 15th European Conference on Antennas and Propagation (EuCAP), 24 Mar. 2021, sec. Po2, pp. 1–4, Dusseldorf, Germany (remote). DOI: 10.23919/EuCAP51087.2021.9411132. [IEEEXplore link]

[14] I. Bashir, D. Leipold, M. Asker, E. Blokhina, D. Redmond, B. Staszewski, A. Esmailiyan, P. Giounanlis, D. Andrademiceli, A. Sokolov, X. Wu, “A 22nm FD-SOI-CMOS Scalable Quantum Processor SoC with Fully Integrated Control Electronics at 3.5K,” American Physical Society (APS) Meeting, 17 Mar. 2021, ses. M30.13, pp. 1–1, USA (remote). [Meeting link]

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2020

[1] G. Wegrzyn, P. Kmon and R. B. Staszewski, “Digital Controller for Multichannel Time to Digital Converter in 28nm CMOS Process” International Students Conf. (ISC), 12 Dec. 2020, pp. 1–1, Poland (remote). [Conference link]

[2] P. Giounanlis, E. Blokhina, A. Sokolov, E. Koskin, I. Bashir, D. Leipold, M. Asker, A. Esmailian, H. Wang, C. Cetintepe, and R. Staszewski, “Electrostatic control and entanglement of silicon qubits in 22nm FDSOI process,” Quantum Technology International Conference (QTech), pp. 1–1, 2 Nov. 2020, Barcelona, Spain. [Conference link]

[3] I. Bashir, D. Leipold, M. Asker, A. Esmailiyan, H. Wang, T. Siriburanon, P. Giounanlis, A. Koziol, E. Blokhina and R. B. Staszewski, “RF clock distribution system for a scalable quantum processor in 22-nm FDSOI operating at 3.8K cryo-genic temperature,” Proc. of IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. Mo4A-4, pp. 215–218, 4–6 Aug. 2020, Los Angeles, CA, USA. DOI: 10.1109/RFIC49505.2020.9218321. [IEEE Xplore link]

[4] R. B. Staszewski, P. Giounanlis, A. Esmailiyan, H. Wang, I. Bashir, C. Cetintepe, D. Andrade-Miceli, M. Asker, D. Leipold, T. Siriburanon, A. Sokolov and E. Blokhina, “Position-based CMOS charge qubits for scalable quantum processors at 4K,” Proc. of IEEE Intl. Symp. on Circuits and Systems (ISCAS), paper 2595, sec. B2L-H, pp. 1–5, 14 Oct. 2020, Seville, Spain. DOI: 10.1109/ISCAS45731.2020.9180789. [IEEE Xplore link]

[5] P. Giounanlis, A. Sokolov, E. Blokhina, I. Bashir, D. Leipold and R. B. Staszewski, “Electrostatic control and entanglement of CMOS position-based qubits,” Proc. of IEEE Intl. Symp. on Circuits and Systems (ISCAS), paper 1980, sec. B1L-H, pp. 1–5, 11–14 Oct. 2020, Seville, Spain. DOI: 10.1109/ISCAS45731.2020.9180721. [IEEE Xplore link]

[6] X. Wu, T. Siriburanon and R. B. Staszewski, “Time-Domain Multiply-Accumulator using Digital-to-Time Multiplier for CNN Processors in 28-nm CMOS,” Proc. of 31 Irish Signals and Systems Conf. (ISSC), 12 Jun. 2020, pp. 1–4, Letterkenny, Ireland. DOI:10.1109/ISSC49989.2020.9180202. [IEEE Xplore link]

[7] F. A. Shiwani, T. Siriburanon, J. Du and R. B. Staszewski, “Charge Analysis in SAR ADC with Discrete-Time Reference Driver,” Proc. of 31 Irish Signals and Systems Conf. (ISSC), 11 Jun. 2020, pp. 1–6, Letterkenny, Ireland. DOI:10.1109/ISSC49989.2020.9180184. [IEEE Xplore link]

[8] D. Watte, Y. Hu, T. Siriburanon and R. B. Staszewski, “Design of a Non-Linear Sized I/Q Digital PA for 5G mm-Wave Communications in 28 nm CMOS,” Proc. of 31 Irish Signals and Systems Conf. (ISSC), 11 Jun. 2020, pp. 1–4, Letterkenny, Ireland. DOI:10.1109/ISSC49989.2020.9180196. [IEEE Xplore link]

[9] A. Sokolov, D. Mishagli, P. Giounanlis, I. Bashir, D. Leipold, E. Koskin, R. B. Staszewski and E. Blokhina, “Simulation Methodology for Electron Transfer in CMOS Quantum Dots,” International Conference on Computational Science (ICCS), in Proc. of Springer Lecture Notes in Computer Science (LNCS) Series, 10 June 2020, paper 331, pp. 1–14, Amsterdam, The Netherlands. DOI: https://doi.org/10.1007/978-3-030-50433-5 50. [DOI link] [Springer link]

[10] E. Blokhina, P. Giounanlis, D. Leipold, I. Bashir, M. Asker, A. Esmailiyan, H. Wang, T. Siriburanon, A. Sokolov and R. Staszewski, “Charge and Hybrid Qubits in 22nm FDSOI process,” American Physical Society (APS) Meeting, 6 Mar. 2020, ses. X17.13, pp. 1–1, Denver, Colorado, USA. [Meeting link] [Slides link]

[11] M. Song, M. Ding, E. Tiurin, K. Xu, E. Allebes, G. Singh, P. Zhang, S. Traferro, H. Korpela, N. van Helleputte, R. B. Staszewski, Y.-H. Liu and C. Bachmann, “A 3.5mmx3.8mm crystal-Less MICS transceiver featuring coverages of ±160ppm carrier frequency offset and 4.8-VSWR antenna impedance for insertable smart pills,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), 19 Feb. 2020, pp. 474–475, sec. 30.8, San Francisco, CA, USA. DOI: 10.1109/ISSCC19947.2020.9063083. [IEEE Xplore link]

[12] Y. Hu, X. Chen, T. Siriburanon, J. Du, Z. Gao, V. Govindaraj, A. Zhu and R. B. Staszewski, “A 21.7–26.5GHz charge-sharing locking quadrature PLL with implicit digital frequency tracking loop achieving 75fs jitter and -250dB FoM,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), 18 Feb. 2020, pp. 276–277, sec. 17.6, San Francisco, CA, USA. DOI: 10.1109/ISSCC19947.2020.9063024. [IEEE Xplore link]

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2019

[1] P. Giounanlis, E. Blokhina, D. Leipold and R. B. Staszewski, “A Python-Verilog toolbox for modeling of a Hadamard gate based on position-based CMOS qubits,” Proc. of 26th IEEE International Conf. on Electronics Circuits and Systems (ICECS), 29 Nov. 2019, ses. C1P-F, pp. 1–4, Genova, Italy. DOI: 10.1109/ICECS46596.2019.8965149. [IEEE Xplore link]

[2] V. Govindaraj, J. Du, Y. Hu, T. Siriburanon and R. B. Staszewski, “DTC-assisted all-digital phase-locked loop exploiting hybrid time/voltage phase digitization,” Proc. of IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 11–14 Nov. 2019, sec. A1L-D, pp. 1–4, Bangkok, Thailand. DOI: 10.1109/APCCAS47518.2019.8953166. [IEEE Xplore link][APCCAS link]

[3] K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold, and R. Staszewski, “Description of interface between semiconductor and superconducting quantum computer,” XIX National Conference on Superconductivity – Unconventional Superconductivity and Strongly Correlated Electron Systems, 10 Oct. 2019, pp. 1–1, Hotel Magellan, Bronislawow, Poland. [Conference link]

[4] G. Nikendish, R. B. Staszewski and A. Zhu, “A broadband continuous class-F GaN MMIC PA using multi-resonance matching network,” Proc. of IEEE European Microwave Integrated Circuits Conference (EuMIC), 30 Sept. 2019, sec. EuMIC08, pp. 108–111, Paris, France. DOI: 10.23919/EuMIC.2019.8909495. [IEEE Xplore link]

[5] G. Nikandish, R. B. Staszewski and A. Zhu, “Broadband fully integrated GaN power amplifier with embedded minimum inductor bandpass filter and AM-PM compensation,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. A3L-C2, pp. 177–180, 24 Sept. 2019, Krakow, Poland. DOI: 10.1109/ESSCIRC.2019.8902513. [IEEE Xplore link]

[6] I. Bashir, M. Asker, C. Cetintepe, D. Leipold, A. Esmailiyan, H. Wang, T. Siriburanon, P. Giounanlis, E. Blokhina, K. Pomorski and R. B. Staszewski, “A mixed-signal control core for a fully integrated semiconductor quantum computer system-on-chip,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. A2L-C4, pp. 125–128, 24 Sept. 2019, Krakow, Poland. DOI: 10.1109/ESSCIRC.2019.8902885. [IEEE Xplore link]

[7] F.-W. Kuo, Z. Zong, H.-N. R. Chen, L.-C. Cho, C.-P. Jou, M. Chen and R. B. Staszewski, “A 77/79-GHz frequency generator in 16-nm CMOS for FMCW radar applications based on a 26-GHz oscillator with co-generated third harmonic,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. A1L-B4, pp. 53–56, 24 Sept. 2019, Krakow, Poland. DOI: 10.1109/ESSCIRC.2019.8902490. [IEEE Xplore link]

[8] M. Atef Shehata, M. Keaveney and R. B. Staszewski, “A 184.6-dBc/Hz FOM 100-kHz flicker phase noise corner 30-GHz rotary travelling-wave oscillator using distributed stubs in 22-nm FD-SOI,” Proc. of IEEE European Solid-State Circuits Conf.(ESSCIRC), sec. A1L-B1, pp. 41–44, 24 Sept. 2019, Krakow, Poland. DOI: 10.1109/ESSCIRC.2019.8902916. [IEEE Xplore link]

[9] K. Pomorski, P. Giounanlis, E. Blokhina, and R. B. Staszewski, “Programmable quantum matter in CMOS electronics,” 7th International Symposium on Integrated Functionalities, 12 Aug. 2019, pp. 1–1, University College Dublin, Dublin, Ireland. [Symposium link]

[10] K. Pomorski, P. Peczkowski, P. Giounanlis, E. Blokhina, R. B. Staszewski and D. Leipold, “Fundamental description of (field induced) Josephson junctions coupling with semiconductor position based electrostatic qubits,” CHATS on Applied Superconductivity, 11 Jul. 2019, pp. 1–1, Faculty of Mechanical Engineering and Mechatronics of the West Pomeranian University of Technology, Szczecin, Poland. [Conference link]

[11] Z. Gao, Y. Hu, T. Siriburanon and R. B. Staszewski, “28GHz quadrature frequency generation exploiting injection locked harmonic extractors for 5G communications,” Proc. of 17th IEEE International NEWCAS Conf. (NEWCAS), 23–26 Jun. 2019, ses. C2L-A, pp. 1–4, Munich, Germany. (3rd Best Paper Award) DOI: 10.1109/NEWCAS44328.2019.8961293. [IEEE Xplore link]

[12] A. Bozorg and R. B. Staszewski, “Two-fold noise-cancelling low-noise amplifier in 28-nm CMOS,” Proc. of 17th IEEE International NEWCAS Conf. (NEWCAS), 23–26 Jun. 2019, ses. C2L-B, pp. 1–4, Munich, Germany. DOI: 10.1109/NEWCAS44328.2019.8961224. [IEEE Xplore link]

[13] I. Bashir, P. Giounanlis, E. Blokhina, D. Leipold, K. Pomorski and R. B. Staszewski, “A Verilog-A model of the shuttle of an electron in a two quantum-dot system,” Proc. of 17th IEEE International NEWCAS Conf. (NEWCAS), 23–26 Jun. 2019, ses. B1PC, pp. 1–4, Munich, Germany. DOI: 10.1109/NEWCAS44328.2019.8961307. [IEEE Xplore link]

[14] K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold and R. B. Staszewski, “Unified description of single electron semiconductor devices and Josephson junction devices in the direction of implementation hybrid semiconductor superconductor quantum computer,” Superconductivity in low-dimensional and interacting systems, 3–6 Jun. 2019, pp. 1–1, Physikzentrum, Bad Honnef, Germany. [Conference link]

[15] K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold, P. Peczkowski and R. B. Staszewski, “From two types of electrostatic position-dependent semiconductor qubits to quantum universal gates and hybrid semiconductor-superconducting quantum computer,” Proceedings of SPIE 11054, Superconductivity and Particle Accelerators (SPAS) conference, 14 May 2019, pp. 1–21. DOI: https://doi.org/10.1117/12.2525217. [SPIE Digital Library (Open Access)]

[16] K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold and R. B. Staszewski, “Towards universal framework for electrostaticqubit-based semiconductor quantum computer and its integration with CMOS electronics and superconducting quantum circuits,” Engineering a Scalable Quantum Information Processor, 24 Apr. 2019, pp. 1–1, Physikzentrum, Bad Honnef, Germany. [Conference link]

[17] J. Du, Y. Hu, T. Siriburanon and R. B. Staszewski, “A 0.3 V, 35% tuning-range, 60 kHz 1/f3-corner digitally controlled oscillator with vertically integrated switched capacitor banks achieving FoMT of -199 dB in 28-nm CMOS,” Proc. of IEEE Custom Integrated Circuits Conf.(CICC), 17 Apr. 2019, ses. 26–4, pp. 1–4, Austin, TX, USA. DOI: 10.1109/CICC.2019.8780295. [IEEE Xplore link]

[18] D. Leipold, H. Leipold, L. Leipold, E. Blokhina, P. Giounanlis, K. Pomorski, R. Staszewski, I. Bashir, G. Maxim, M. Asker, C.Cetintepe, A. Esmailiyan, H.Wang and T. Siriburanon, “Implementation and Simulation of Electrostatically Controlled Quantum Dots in CMOS Technology,” American Physical Society (APS) Meeting, 6 Mar. 2019, ses. P35.12, pp. 1–1, Boston, Massachusetts, USA. [Meeting link]

[19] K. Pomorski, P. Giounanlis, E. Blokhina, R. B. Staszewski and D. Leipold, “Modeling quantum universal gates in semiconductor CMOS,” Scalable Hardware Platforms for Quantum Computing, 17 Jan. 2019, pp. 1–1, Physikzentrum, Bad Honnef, Germany. [Conference link]

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2018

[1] Giounanlis, E. Blokhina, D. Leipold, and R. B. Staszewski, “Occupancy oscillations and electron transfer in multiple-quantumdot qubits and their circuit representation,” Proc. of 25th IEEE International Conf. on Electronics Circuits and Systems (ICECS),10 Dec. 2018, ses. A4L-D, pp. 153–156, Bordeaux, France. DOI: 10.1109/ICECS.2018.8618063. [IEEE Xplore link]

[2] K. Pomorski, P. Peczkowski, P. Prokopow, A. Fujimaki and R. B. Staszewski, “Towards modelling and implementation of superconduting and semicondutor classical and quantum mind,” Superconductivity and Particle Accelerators (SPAS) conference, 29 Nov. 2018, ses. XII, pp. 1–1, Krakow, Poland. [Conference link] [Abstract book link]

[3] K. Xu, J. Yin, P.-I. Mak, R. B. Staszewski and R. P. Martins, “A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA ,” Proc. of IEEE Asian Solid-State Circuits Conf. (A-SSCC), 7 Nov. 2018, sec. 21–2, pp. 293–294, Tainan, Taiwan. DOI: 10.1109/ASSCC.2018.8579322. [IEEE Xplore link]

[4] U. Kamath, T. Yu, W. Yao, E. Cullen, J. Jennings, Susan Wu and R. B. Staszewski, “BJT device and circuit co-optimization enabling bandgap reference and temperature sensing in 7-nm FinFET,” Proc. of IEEE European Solid-State Devices Conf. (ESSDERC), sec. A6L-E3 pp. 86–89, 4 Sept. 2018, Dresden, Germany. DOI: 10.1109/ESSDERC.2018.8486902. [IEEE Xplore link]

[5] U. Kamath, E. Cullen, J. Jennings, I. Cical, D. Walsh and R. B. Staszewski, “A 1V bandgap reference in 7-nm FinFET with a programmable temperature coefficient and an inaccuracy of ±0.2% from -45℃ to 125℃,” Proc. of IEEE European Solid-State Circuits Conf.(ESSCIRC), sec. A6L-A1, pp. 78–81, 4 Sept. 2018, Dresden, Germany. DOI: 10.1109/ESSCIRC.2018.8494284. [IEEE Xplore link]

[6] P. Chen, X. Huang, Y. Chen, L. Wu and R. B. Staszewski, “An on-chip self-characterization of a digital-to-time converter by embedding it in a first-order ΔΣ loop” IEEE International Symposium on Integrated Circuits and Systems (ISICAS), 3 Sept. 2018, pp. 3734–3744, Taormina, Italy. DOI: 10.1109/TCSI.2018.2857999. [IEEE Xplore link (Open Access)]

[7] F.-W. Kuo, M. Babaie, H.-N. R. Chen, L.-C. Cho, C.-P. Jou, M. Chen and R. B. Staszewski, “An all-digital PLL for cellular mobile phones in 28 nm CMOS with -55 dBc fractional and -91 dBc reference spurs”, IEEE International Symposium on Integrated Circuits and Systems (ISICAS), 3 Sept. 2018, pp. 3756–3768, Taormina, Italy. DOI: 10.1109/TCSI.2018.2855972. [IEEE Xplore link (Open Access)]

[8] M. Keshavarz Hedayati, A. Abdipour, R. Sarraf Shirazi, C. Cetintepe and R. B. Staszewski, “A 33-GHz LNA for 5G wireless systems in 28-nm bulk CMOS” IEEE International Symposium on Integrated Circuits and Systems (ISICAS), 3 Sept. 2018, 1460–1464, Taormina, Italy. DOI: 10.1109/TCSII.2018.2859187. [IEEE Xplore link (Open Access)]

[9] Z. Zong and R. B. Staszewski, “Effects of subharmonics in LO generation on RF transceivers”, IEEE MTT-S International Microwave Workshop Series on 5G Hardware and System Technologies (IMWS-5G), 30 Aug. 2018, sec. 3–3, pp. 1–3, Dublin, Ireland. DOI: 10.1109/IMWS-5G.2018.8484718. [IEEE Xplore link]

[10] M. Salarpour, R. B. Staszewski and F. Faraneh, “A mm-wave MIMO transmitter with a digital beam steering capability using CMOS all-digital phase-locked loop chips”, IEEE MTT-S International Microwave Workshop Series on 5G Hardware and System Technologies (IMWS-5G), 30 Aug. 2018, sec. 1–3, Dublin, Ireland. DOI: 10.1109/IMWS-5G.2018.8484613. [IEEE Xplore link]

[11] J. Szyduczynski, V. Nguyen, F. Schembari, R. B. Staszewski, M. Miskowicz and Dariusz Koscielnik, “Behavioral Modelling and Optimization of a Feedback Successive Approximation TDC with Dynamic Delay Equalization,” Proc. of 4th IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP), 29 June 2018, pp. 1–6, Perpignan, France.

[12] T.-H. Tsai, R.-B. Sheen, C.-H. Chang and R. B. Staszewski, “A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7nm FinFET CMOS Featuring 0.619ps Integrated Jitter and 0.6us Settling Time at 2.3mW,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 21 June 2018, sec. C17.3, pp. 183–184, Honolulu, HI, USA. DOI: 10.1109/VLSIC.2018.8502274. [IEEE Xplore link]

[13] F.-W. Kuo, S. Binsfeld Ferreira, R. Chen, L.-C. Cho, C.-P. Jou, M. Chen, M. Babaie and R. B. Staszewski, “Towards ultra-low-voltage and ultra-low-power discrete-time receivers for Internet-of-Things,” Proc. of IEEE International Microwave Symp. (IMS), 14 June 2018, sec. Th1F, pp. 1–3, Philadelphia, Pennsylvania, USA. USA. DOI: 10.1109/MWSYM.2018.8439369. [IEEE Xplore link]

[14] M. Salarpour, F. Farzaneh and R. B. Staszewski, “ Design procedure of a U-slot patch antenna array for 60 GHz MIMO applica-tion,” ,Proc. of 14th IEEE International Conference on Advanced Trends in Radioelectronics, Telecommunications and Computer Engineering (TCSET), 21 Feb 2018, sec. S6, pp. 1–4, Lviv-Slavske, Ukraine. DOI: 10.1109/TCSET.2018.8336276. [IEEE Xplore link]

[15] M.-S. Yuan, C.-C. Li, C.-C. Liao, Y.-T. Lin, C.-H. Chang and R. B. Staszewski, “A 0.45V sub-mW all-digital PLL in 16nm FinFET for Bluetooth Low-Energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), 14 Feb. 2018, pp. 448–449, sec. 28.4, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2018.8310377. [IEEE Xplore link]

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2017

[1] Y. Chen, M. Babaie and R. B. Staszewski, “A 350-mV 2.4GHz Quadrature Oscillator with Nearly Instantaneous Start-Up Using Series LC Tanks,” Proc. of IEEE Asian Solid-State Circuits Conf. (A-SSCC), 7 Nov. 2017, sec. A2L-D4, pp. 105–108, Seoul, Korea. DOI: 10.1109/ASSCC.2017.8240227. [IEEE Xplore link]

[2] P. Chen, F. Zhang, Z. Zong, H. Zheng, T. Siriburanon and R. B. Staszewski, “A 15-uW, 103-fs step, 5-bit capacitor DAC-based constant-slope digital-to-time converter in 28nm CMOS,” Proc. of IEEE Asian Solid-State Circuits Conf. (A-SSCC), 7 Nov. 2017, sec. A2L-D1, pp. 93–96, Seoul, Korea. DOI: 10.1109/ASSCC.2017.8240224. [IEEE Xplore link]

[3] Y. Hu, T. Siriburanon and R. B. Staszewski, “A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120kHz 1/f3 corner,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. A4L-C1, pp. 87–90, 12 Sept. 2017,Leuven, Belgium. DOI: 10.1109/ESSCIRC.2017.8094532. [IEEE Xplore link]

[4] F.-W. Kuo, S. Pourmousavian, T. Siriburanon, R. Chen, L.-C. Cho, C.-P. Jou, F.-L. Hsueh and R. B. Staszewski, “A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 7 June 2017, sec. C14.1, pp. 178–179, Kyoto, Japan. DOI: 10.23919/VLSIC.2017.8008472. [IEEE Xplore link]

[5] L.-C. Cho, F.-W. Kuo, R. Chen, J. Liu, C.-P. Jou, F.-L. Hsueh and R. B. Staszewski, “A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), 7 June 2017, sec. 10.4, pp. 130–131, Kyoto, Japan. DOI: 10.23919/VLSIC.2017.8008457. [IEEE Xplorelink]

[6] H. Wang, F. Schembari, R. B. Staszewski and M. Miskowicz, “Frequency-domain adaptive-resolution level-crossing sampling ADC,” Proc. of IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017),24 May 2017, pp. 1–4, Funchal, Madeira, Portugal. DOI: 10.1109/EBCCSP.2017.8022825. [IEEE Xplore link]

[7] V. Nguyen, F. Schembari and R. B. Staszewski, “Oscillator-based ADCs: An exploration of time-mode analog-to-digital conversion,” Proc. of IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), 24 May 2017, pp. 1–4, Funchal, Madeira, Portugal. DOI: 10.1109/EBCCSP.2017.8022829. [IEEE Xplore link]

[8] F. Zhang, P. Chen, A. Zhu and R. B. Staszewski, “A highly power-efficient digital mixing RFDAC,” Proc. of Research Colloquium of Royal Irish Academy (RIA) on Radio Science and Communications for a Smarter World, ssec. 1.2, pp. 1–4, 9 Mar. 2017, Dublin, Ireland.

[9] Y.-H. Liu, V. K. Purushothaman, C. Lu, J. Dijkhuis, R. B. Staszewski, C. Bachmann and K. Philips, “A 770pJ/b 0.85V 0.3mm2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications,” Proc. of IEEE Solid-State Circuits Conf.(ISSCC), sec. 24.1, pp. 408–409, 8 Feb. 2017, San Francisco, CA, USA. DOI:10.1109/ISSCC.2017.7870434. [IEEE Xplore link]

[10] C.-C. Li, M.-S. Yuan, C.-H. Chang, Y.-T. Lin, K. Hsieh, M. Chen, and R. B. Staszewski, “A 0.2V trifilar-coil DCO with an energy harvesting DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution and frequency pushing of 38MHz/V, ” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), sec. 19.6, pp. 332–333, 8 Feb. 2017, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2017.7870396. [IEEE Xplore link]

[11] E. Charbon, F. Sebastiano, M. Babaie, A. Vladimirescu, M. Shahmohammadi, R. B. Staszewski, H. A.R. Homulle, B. Patra, J. P.G. van Dijk, R. M. Incandela, L. Song and B. Valizadehpasha, “Cryo-CMOS circuits and systems for scalable quantum computing, ” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), sec. 15.5, pp. 264–265, 7 Feb. 2017, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2017.7870362. [IEEE Xplore link]

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2016

[1] M. Keshavarz Hedayati, A. Abdipour, R. S. Shirazi, M. John, M. J. Ammann and R. B. Staszewski, “A 38 GHz on-chip antenna in 28-nm CMOS using artificial magnetic conductor for 5G wireless systems,” Proc. of IEEE Millimeter-Wave and Terahertz Technologies Conf. (MMWATT), ses. 7B, pp. 1–4, 21 Dec. 2016, Tehran, Iran. DOI: 10.1109/MMWaTT.2016.7869869. [IEEE Xplore link]

[2] Y. Wu, M. Shahmohammadi, Y. Chen, P. Lu and R. B. Staszewski, “A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise, ” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. A3L-J4, pp. 356–359, 13 Sept. 2016, Lausanne, Switzerland. DOI: 10.1109/ESSCIRC.2016.7598279. [IEEE Xplore link]

[3] C.-C. Li, T.-H. Tsai, M.-S. Yuan, C.-C. Liao, C.-H. Chang, T.-C. Huang, H.-Y. Liao, C.-T. Lu, H.-Y. Kuo, K. Hsieh, M. Chen, A. Ximenes and R. B. Staszewski, “A 0.034mm2, 725fs rms Jitter, 1.8%/V frequency-pushing, 10.8–19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), sec. 22.5, pp. 240–241, 17 June 2016, Honolulu, HI, USA. DOI: 10.1109/VLSIC.2016.7573551. [IEEE Xplore link]

[4] F.-W. Kuo, S. Binsfeld Ferreira, M. Babaie, R. Chen, L.-C. Cho, C.-P. Jou, F.-L. Hsueh, G. Huang, I. Madadi, M. Tohidian and R. B. Staszewski, “A Bluetooth Low-Energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), sec. 7.1, pp. 64–65, 15 June 2016, Honolulu, HI, USA. DOI: 10.1109/VLSIC.2016.7573480. [IEEE Xplore link]

[5] Y. Wu and R. B. Staszewski, “A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time-amplifier based two-step flash-time-to-digital converter,” Proc. of IEEE International Nordic-Mediterranean Workshop on Time-to-Digital Converters and Applications (NoMe - TDC 2016), pp. 1–4, 15 June 2016, Krakow, Poland. DOI: 10.1109/EBCCSP.2016.7605282. [IEEE Xplore link]

[6] P. Chen and R. B. Staszewski, “Exponential extended flash time-to-digital converter,” Proc. of IEEE International Nordic-Mediterranean Workshop on Time-to-Digital Converters and Applications (NoMe - TDC 2016), pp. 1–4, 15 June 2016, Krakow, Poland. DOI: 10.1109/EBCCSP.2016.7605281. [IEEE Xplore link]

[7] Z. Hu, L.C.N. de Vreede, M. S. Alavi, D. A. Cavillo-Cortes, R. B. Staszewski and S. He, “A 5.9 GHz RFDACbased outphasing power amplifier in 40-nm CMOS with 49.2% efficiency and 22.2 dBm power,” Proc. of IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO3D-3, pp. 206–209, 23 May 2016, San Francisco, CA, USA. DOI: 10.1109/RFIC.2016.7508287. [IEEE Xplore link]

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2015

[1] F.-W. Kuo, M. Babaie, R. Chen, K. Yen, J.-Y. Chien, L. Cho, F. Kuo, C.-P. Jou, F.-L. Hsueh and R. B. Staszewski, “A fully integrated 28nm Bluetooth low-energy transmitter with 36% system efficiency at 3dBm,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. C2L-B, pp. 356–359, 17 Sept. 2015, Graz, Austria. DOI: 10.1109/ESSCIRC.2015.7313901. [IEEE Xplore link]

[2] P. Chen, X. Huang, Y.-H. Liu, M. Ding, C. Zhou, A. Ba, K. Philips, H. de Groot and R. B. Staszewski, “Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs,” Proc. of IEEE European Solid-State Circuits Conf. (ESSCIRC), sec. B5L-A, pp. 283–286, 16 Sept. 2015, Graz, Austria. DOI: 10.1109/ESSCIRC.2015.7313882. [IEEE Xplore link]

[3] I. Madadi, M. Tohidian, K. Cornelissens, P. Vandenameele and R. B. Staszewski, “A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS,” Proc. of IEEE Symp. on VLSI Circuits (VLSI), sec. 22.4, pp. C08–C09, 19 June 2015, Kyoto, Japan. DOI: 10.1109/VLSIC.2015.7231302. [IEEE Xplore link]

[4] P. Chen, X.-C. Huang and R. B. Staszewski, “Fractional spur suppression in all-digital phase-locked loops,” Proc. of IEEE Intl. Symp. on Circuits and Systems (ISCAS), paper 2597, sec. C4L-B, pp. 2565–2568, 27 May 2015, Lisbon, Portugal. DOI: 10.1109/ISCAS.2015.7169209. [IEEE Xplore link]

[5] B. Wang, Y.-H. Liu, P. Harpe, J. vd Heuvel, B. Liu, H. Gao, P. Baltus and R. B. Staszewski, “A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS,” Proc. of IEEE Intl. Symp. on Circuits and Systems (ISCAS), paper 1509, sec. C2P-V, pp. 2289–2292, 27 May 2015, Lisbon, Portugal. DOI: 10.1109/ISCAS.2015.7169140. [IEEE Xplore link]

[6] X. Luo, H. Qian and R. B. Staszewski, “A waveform-shaping millimeter-wave oscillator with 184.7dBc/Hz FOM in 40nm digital CMOS process,” Proc. of 2015 IEEE International Microwave Symp. (IMS), sec. TU4H-1, pp. 1–3, 19 May 2015, Phoenix, Arizona, USA. DOI: 10.1109/MWSYM.2015.7167075 [IEEE Xplore link]

[7] A. Tavakol and R. B. Staszewski, “An CMOS impedance sensor for MEMS adaptive antenna matching,” Proc. of IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RTU–IF6-2, pp. 379–382, 19 May 2015, Phoenix, Arizona, USA. DOI: 10.1109/RFIC.2015.7337784. [IEEE Xplore link]

[8] Z. Zong, M. Babaie and R. B. Staszewski, “A 60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoM,” Proc. of 2015 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RTU-1-A-5, pp. 279–282, 18 May 2015, Phoenix, Arizona, USA. DOI: 10.1109/RFIC.2015.7337759. [IEEE Xplore link]

[9] M. Babaie, R. B. Staszewski, L. Galatro and M. Spirito, “A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS,” Proc. of IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO-4-B-4, pp. 215–218, 18 May 2015, Phoenix, Arizona, USA. DOI: 10.1109/RFIC.2015.7337743. [IEEE Xplore link]

[10] M. Babaie, M. Shahmohammadi and R. B. Staszewski, “A 0.5V 0.5mW switching current source oscillator,” Proc. of 2015 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec.RMO-4-A-1, pp. 183–186, 18 May, Phoenix, Arizona, USA. DOI: 10.1109/RFIC.2015.7337735. [IEEE Xplore link]

[11] Y. Wu, P. Lu and R. B. Staszewski, “A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-todigital converter for ADPLL,” Proc. of 2015 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO-2-C-2, pp. 95–98, 18 May 2015, Phoenix, Arizona, USA. DOI: 10.1109/RFIC.2015.7337713. [IEEE Xplore link]

[12] M. Shahmohammadi, M. Babaie and R. B. Staszewski, “A 1/f noise upconversion reduction technique applied to class-D and class-F oscillators,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), sec. 25.4, pp. 444–445, 25 Feb. 2015, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2015.7063117.[IEEE Xplore link]

[13] T.-H. Tsai, M.-S. Yuan, C.-H. Chang, C.-C. Liao, C.-C. Li and R. B. Staszewski, “A 1.22ps integrated-jitter 0.25- to-4GHz fractional-N ADPLL in 16nm FinFET CMOS,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), sec. 14.5, pp. 260–261, 24 Feb. 2015, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2015.7063025.[IEEE Xplore link]

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2014

[1] I. E. Lager, R. B. Staszewski, A. B. Smolders and D.M.W. Leenaerts, “Ultra-high data-rate wireless transfer in a saturated spectrum - new paradigms,” Proc. of IEEE European Microwave Week (EuMW) Conference, sec. EuMC47, pp. 917–920, 9 Oct. 2014, Fiera di Roma, Italy. DOI: 10.1109/EuMC.2014.6986585. [IEEE Xplore link]

[2] W. Wu, R. B. Staszewski and J. R. Long, “Design for test of a mm-wave ADPLL-based transmitter,” (Invited), Proc. of IEEE Custom Integrated Circuits Conf. (CICC), ses. 14–1, pp. 1–8, 16 Sept. 2014, San Jose, CA, USA. DOI: 10.1109/CICC.2014.6945994. [IEEE Xplore link]

[3] A. Visweswaran, J. R. Long and R. B. Staszewski, “A 1.2V 110-MHz-UGB differential class-AB amplifier in 65nm CMOS,” Proc. of IEEE Custom Integrated Circuits Conf. (CICC), ses. 8–4, pp. 1–4, 16 Sept. 2014, San Jose, CA, USA. DOI:10.1109/CICC.2014.6946066. [IEEE Xplore link]

[4] F.-W. Kuo, R. Chen, K. Yen, H.-Y. Liao, C.-P. Jou, F.-L. Hsueh, M. Babaie and R. B. Staszewski, “A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS,” Proc. of 2005 IEEE Symp. on VLSI Circuits (VLSI), sec. 9.4, pp. 1–2, 12 June 2014, Honolulu, USA. DOI: 10.1109/VLSIC.2014.6858393. [IEEE Xplore link]

[5] A. Ba, V. K. Chillara, Y. Liu, K. Philips and R. B. Staszewski, “A 2.4GHz class-D power amplifier with conduction angle calibration for -50dBc harmonic emissions,” Proc. of 2014 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO4B-3, pp. 239–242, 2 June 2014, Tampa, Florida, USA. DOI: 10.1109/RFIC.2014.6851708. [IEEE Xplore link]

[6] V. K. Chillara, Y.-H. Liu, B. Wang, A. Ba, M. Vidojkovic, K. Philips, H. de Groot and R. B. Staszewski, “An 860µW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), sec. 9.8, pp. 172–173, 11 Feb. 2014, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2014.6757387. [IEEE Xplore link]

[7] M. Tohidian, I. Madadi and R. B. Staszewski, “A fully integrated highly reconfigurable discrete-time super-heterodyne receiver,”Proc. of IEEE Solid-State Circuits Conf. (ISSCC), sec. 3.8, pp. 72–73, 10 Feb. 2014, San Francisco, CA, USA. DOI:10.1109/ISSCC.2014.6757343. [IEEE Xplore link]

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2013

[1] S.A.R.A. Mehr, M. Tohidian and R. B. Staszewski, “Frequency translation through fractional divider for two-channel pulling mitigation,” Proc. of IEEE 2013 European Solid-State Circuits Conference (ESSCIRC’13), sec. B3L-D, pp. 241–244, 18 Sept. 2013, Bucharest, Romania. DOI: 10.1109/ESSCIRC.2013.6649117. [IEEE Xplore link]

[2] J.-C. Zhuang and R. B. Staszewski, “Gain estimation of a digital-to-time converter for phase-prediction all-digital PLL,” Proc. of IEEE 21th European Conference on Circuit Theory and Design (ECCTD’13), paper 122, pp. 1–4, 11 Sept. 2013, Dresden, Germany. DOI:10.1109/ECCTD.2013.6662211. [IEEE Xplore link]

[3] M. Babaie and R. B. Staszewski, “A study of RF oscillator reliability in nanoscale CMOS,” Proc. of IEEE 21th European Conference on Circuit Theory and Design (ECCTD’13), paper 114, pp. 1–4, 11 Sept. 2013, Dresden, Germany. DOI: 10.1109/ECCTD.2013.6662205. [IEEE Xplore link]

[4] I. Madadi, M. Tohidian and R. B. Staszewski, “A 65nm CMOS High-IF Superheterodyne Receiver with a High-Q Complex BPF,” Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RTU2A–3, pp. 323–326, 4 June 2013, Seattle, USA. DOI: 10.1109/RFIC.2013.6569594. [IEEE Xplore link]

[5] M. Tohidian, S.A.R.A. Mehr and R. B. Staszewski, “Dual-Core High-Swing Class-C Oscillator with Ultra-Low Phase Noise,” Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. , sec. RMO4C–4, pp. 243–246, 3 June 2013, Seattle, USA. [IEEE Xplore link]

[6] A. Visweswaran, J. R. Long, L. Galatro, M. Spirito and R. B. Staszewski, “An FM Demodulator Operating Across 2-10GHz IF,” Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. , sec. RMO4A–1, pp. 213–216, 3 June 2013, Seattle, USA. DOI: 10.1109/RFIC.2013.6569564. [IEEE Xplore link]

[7] M. Mehrpoo and R. B. Staszewski, “A Highly Selective LNTA Capable of Large-Signal Handling for RF Receiver Front-End,” Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. , sec. RMO3B–4, pp. 185–188, 3 June 2013, Seattle, USA. DOI:10.1109/RFIC.2013.6569556. [IEEE Xplore link]

[8] M. S. Alavi, G. Voicu, R. B. Staszewski, L.C.N. de Vreede and J. R. Long, “A 12-bit Digital I/Q RF-DAC in 65-nm CMOS,” Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. , sec. RMO3A–5, pp. 167–170, 3 June 2013, Seattle, USA. This paper received The Best Student Paper Award- 2nd Place. DOI: 10.1109/RFIC.2013.6569551. [IEEE Xplore link]

[9] W. Wu, X. Bai, R. B. Staszewski and J. R. Long, “A mm-Wave FMCW Radar Transmitter Based on a Multirate ADPLL,” Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,sec.RMO2C–1, pp.107–110,3June2013,Seattle, USA. DOI:10.1109/RFIC.2013.6569535. [IEEE Xplore link]

[10] M. Babaie, A. Visweswaran, Z. He and R. B. Staszewski, “Ultra-Low Phase Noise 7.2-8.7 GHz Clip-and-Restore Oscillator with 191 dBc/Hz FoM,” Proc. of 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symp. , sec. RMO1C–5, pp. 43–46, 3 June 2013, Seattle, USA. DOI: 10.1109/RFIC.2013.6569517. [IEEE Xplore link]

[11] W. Wu, X. Bai, R. B. Staszewski and J. R. Long, “A 56.4-63.4GHz spuriousfree all-digital fractional-N PLL in 65nm CMOS,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), sec. 20.4, pp. 352–353,20 Feb. 2013, San Francisco, CA, USA. DOI:10.1109/ISSCC.2013.6487766. [IEEE Xplore link]

[12] M. Babaie and R. B. Staszewski, “Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS class-F oscillator with 192dBc/Hz FoM,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC) , sec. 20.2, pp. 348–349, 20 Feb. 2013, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2013.6487764. [IEEE Xplore link]

[13] J.-W. Lai, C.-H. Wang, K. Kao, A. Lin, Y.-H. Cho, L. Cho, M.-H. Hung, X.-Y. Shih, C.-M. Lin, S.-H. Yan, Y.-H. Chung, P. Liang, G.-K. Deng, H.-S. Li, G. Chien and R. B. Staszewski, “A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency class-D DPA in 40nm CMOS,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC), sec. 19.8, pp. 342–343, 20 Feb. 2013, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2013.6487762. [IEEE Xplore link]

[14] M. Tohidian, I. Madadi and R. B. Staszewski, “A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS,” Proc. of IEEE Solid-State Circuits Conf. (ISSCC) , sec. 10.2, pp. 174–175, 19 Feb. 2013, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2013.6487687. [IEEE Xplore link]

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2012

[1] P. Kumar, E. Charbon, R. B. Staszewski and A. Borowski, “Low power timeof-light 3D imager system in standard CMOS,” Proc. of 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS’12), ses. C4L-A, pp. 941–944, Seville, Spain, Dec. 2012. DOI: 10.1109/ICECS.2012.6463506. [IEEE Xplore link]

[2] J. Zhuang and R. B. Staszewski, “A low-power all-digital PLL architecture based on phase prediction,” Proc. of 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS’12), ses. C2L–A, pp. 797–800, Seville, Spain, Dec. 2012. DOI: 10.1109/ICECS.2012.6463539. [IEEE Xplore link]

[3] W. Jiang, A. Tavakol, P. Effendrik, M. van de Gevel, F. Verwaal and R. B. Staszewski, “Design of ADPLL system for WiMAX applications in 40-nm CMOS,” Proc. of 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS’12), ses. A1L–D, pp. 73–76, Seville, Spain, Dec. 2012. DOI: 10.1109/ICECS.2012.6463568. [IEEE Xplore link]

[4] A. Visweswaran, R. B. Staszewski, J. R. Long and A. Akhnoukh, “Fine frequency tuning using injection-control in a 1.2V 65nm CMOS quadrature oscillator,” Proc. of 2012 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RTU1A–1, pp. 293–296, 19 June 2012, Montreal, Canada. DOI: 10.1109/RFIC.2012.6242284. [IEEE Xplore link]

[5] W. Wu, J. R. Long, R. B. Staszewski and J. J. Pekarik, “High-resolution 60-GHz DCOs with reconfigurable distributed metal capacitors in passive resonators,” Proc. of 2012 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO2A–5, pp. 91–94, 18 June 2012, Montreal, Canada. DOI: 10.1109/RFIC.2012.6242239. [IEEE Xplore link]

[6] A. Visweswaran, R. B. Staszewski and J. Long, “A clip-and-restore technique to reduce phase noise in a 1.2V 65nm CMOS oscillator for cellular mobile and basestation applications,” Proc. of IEEE Solid-State Circuits Conf., sec. 20.5, pp. 350–351, 22 Feb. 2012, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2012.6177042. [IEEE Xplore link]

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2011

[1] J. Mehta, R. B. Staszewski, G. Feygin, O. Eliezer, M. Frechette and P. Balsara, “Mismatch considerations in an RF–DAC design for a digital polar EDGE transmitter,” Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf., sec. FR1A–4, pp. 169–172, 2 Dec. 2011, Beijing, China. DOI: 10.1109/RFIT.2011.6141743. [IEEE Xplore link]

[2] R. B. Staszewski and M. S. Alavi, “Digital I/Q RF transmitter using time-division duplexing,” Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf., sec. FR1A–3, pp. 165–168, 2 Dec. 2011, Beijing, China. DOI: 10.1109/RFIT.2011.6141744. [IEEE Xplore link]

[3] M. S. Alavi, R. B. Staszewski, L. C.N. de Vreede and J. R. Long, “Orthogonal summing and power combining network in a 65-nm all-digital RF I/Q modulator,” Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf., sec. TH1A–2, pp. 21–24, 1 Dec. 2011, Beijing, China. (Best Paper Award) DOI: 10.1109/RFIT.2011.6141758. [IEEE Xplore link]

[4] R. B. Staszewski, “Digital RF and digitally-assisted RF (invited),” Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf., sec. K–2, pp. 9–16, 30 Nov. 2011, Beijing, China. DOI: 10.1109/RFIT.2011.6141746. [IEEE Xplore link]

[5] M. S. Alavi, A. Visweswaran, R. B. Staszewski, L. C. N. de Vreede, J. R. Long and A. Akhnoukh, “A 2-GHz digital I/Q modulator in 65-nm CMOS,” Proc. of IEEE Asian Solid-State Circuits Conf. (ASSCC), sec. 11–3, pp. 277–280, 16 Nov. 2011, Jeju, Korea. DOI: 10.1109/ASSCC.2011.6123565. [IEEE Xplore link]

[6] R. B. Staszewski, “Digital RF architectures for wireless transceivers (invited),” Proc. of IEEE 20th European Conference on Circuit Theory and Design (ECCTD’11), sec. PLEN4.1, pp. 438–445, Linkoping, Sweden, 30 Aug. 2011. DOI: 10.1109/ECCTD.2011.6043379. [IEEE Xplore link]

[7] P. Effendrik, W. Jiang, M. van de Gevel, F. Verwaal and R. B. Staszewski, “Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS,” Proc. of IEEE 20th European Conference on Circuit Theory and Design (ECCTD’11), sec. T11.4, pp. 370–373, Linkoping, Sweden, 30 Aug. 2011. DOI: 10.1109/ECCTD.2011.6043362. [IEEE Xplore link]

[8] R. B. Staszewski, I. Bashir and K. Waheed, “Dynamic bandwidth adjustment of an RF all-digital PLL,” Proc. of 2011 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO4D-2, pp. 311–314, June 2011, Baltimore, MD, USA. DOI: 10.1109/RFIC.2011.5940658. [IEEE Xplore link]

[9] O. Eliezer, B. Staszewski and S. Vemulapalli, “Digitally controlled oscillator in a 65nm GSM/EDGE transceiver with built-in compensation for capacitor mismatches,” Proc. of 2011 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RTUIF–22, pp. 533–536, June 2011, Baltimore, MD, USA. DOI: 10.1109/RFIC.2011.5940709. [IEEE Xplore link]

[10] I. Bashir and R. B. Staszewski, “Autonomous predistortion calibration of an RF power amplifier,” Proc. of 2011 IEEE Intl. Symp. on Circuits and Systems, paper 2197, sec. A1L-L, pp. 205–208, 16 May 2011, Rio de Janeiro, Brazil. DOI: 10.1109/ISCAS.2011.5937537. [IEEE Xplore link]

[11] R. B. Staszewski, “All-digital RF frequency modulation,” Proc. of 2011 IEEE Intl. Symp. on Circuits and Systems, paper 2475, sec. A2L–J, pp. 426–429, 16 May 2011, Rio de Janeiro, Brazil. DOI: 10.1109/ISCAS.2011.5937593. [IEEE Xplore link]

[12] R. B. Staszewski, K. Waheed, S. Vemulapalli, F. Dulger, J. Walberg, C.-M. Hung and O. Eliezer, “Spur-free all-digital PLL in 65nm for mobile phones,” Proc. of IEEE Solid-StateCircuits Conf.,sec.3.1,pp.52–53,Feb.2011,San Francisco,CA,USA.DOI: 10.1109/ISSCC.2011.5746215. [IEEE Xplore link]

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2010

[1] O. Eliezer, B. Staszewski, J. Mehta, F. Jabbar and I. Bashir, “Accurate self-characterization of mismatches in a capacitor array of a digitally-controlled oscillator,” Proc. of IEEE Dallas Circuits and Systems Workshop (DCAS-10):Design Automation, Methodologies and Manufacturability, pp. 1–4,Oct. 2010, Dallas, TX, USA. DOI: 10.1109/DCAS.2010.5955030. [IEEE Xplore link]

[2] J. Mehta, I. Bashir, V. Zoicas, Y. Wang, O. Eliezer, K. Waheed, M. Entezari, S. Larson, D. Shrestha, S. Rezeq, R. B. Staszewski and P. Balsara, “Self-calibration of a power pre-amplifier in a digital polar transmitter,” Proc. of IEEE Dallas Circuits and Systems Workshop (DCAS-10): Design Automation, Methodologies and Manufacturability, pp. 1–4, Oct. 2010, Dallas, TX, USA. DOI: 10.1109/DCAS.2010.5955042. [IEEE Xplore link]

[3] K. Waheed, M. Sheba, R. B. Staszewski, F. Dulger and S.D. Vamvakos, “Spurious free time-to-digital conversion in an ADPLL using short dithering sequences,” Proc. of 2010 IEEE Custom Integrated Circuits Conf., sec. 12.6 pp. 1–4, Sept. 2010, San Jose, CA, USA. DOI: 10.1109/CICC.2010.5617430. [IEEE Xplore link]

[4] O. Eliezer, R. B. Staszewski and D. Mannath, “A statistical approach for design and testing of analog circuitry in low-cost SoCs,” Proc. of 53rd IEEE Int'l Midwest Symp. on Circuits and Systems, session B1L–B, pp. 461–464, Aug. 2010, Seattle, WA, USA. DOI: 10.1109/MWSCAS.2010.5548733. [IEEE Xplore link]

[5] R. B. Staszewski, “State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS,” Proc. of 2010 IEEE Intl. Symp. on Circuits and Systems,sec. 16.9, pp. 229–232, May 2010, Paris, France. DOI: 10.1109/ISCAS.2010.5537937. [IEEE Xplore link]

[6] R. B. Staszewski, S. Vemulapalli and K. Waheed, “An all-digital offset PLL architecture,” Proc. of 2010 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO1A-3, pp. 17–20, May 2010, Anaheim, CA, USA. DOI: 10.1109/RFIC.2010.5477376. [IEEE Xplore link]

[7] I. Bashir, R. B. Staszewski, O. Eliezer, K. Waheed, V. Zoicas, N. Tal, J. Mehta, M.-C. Lee, P. T. Balsara, and B. Banerjee, “An EDGE transmitter with mitigation of oscillator pulling,” Proc. of 2010 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO1A–2, pp. 13–16, May 2010, Anaheim, CA, USA. DOI: 10.1109/RFIC.2010.5477247. [IEEE Xplore link]

[8] J. Mehta, R. B. Staszewski, O. Eliezer, S. Rezeq, K. Waheed, M. Entezari, G. Feygin, S. Vemulapalli, V. Zoicas, C.-M. Hung, N. Barton, I. Bashir, K. Maggio, M. Frechette, M.-C. Lee, J. Walberg, P. Cruise and N. Yanduru, “A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC,” Proc. of IEEE Solid-State Circuits Conf., sec. 3.2, pp. 58–59, Feb. 2010, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2010.5434050. [IEEE Xplore link]

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2009

[1] W.-H. Wu, J. R. Long and R. B. Staszewski, “A digital ultra-fast acquisition linear frequency modulated PLL for mm-wave FMCW radars,” Proc. of IEEE Symp. on Radio-Frequency Integration Technology (RFIT) Conf., sec. TH1B–3, pp. 32–35, Dec. 2009, Singapore. DOI: 10.1109/RFIT.2009.5383695. [IEEE Xplore link]

[2] O. E. Eliezer, R. B. Staszewski and P. T. Balsara, “A methodological approach for the minimization of self-interference effects in highly integrated transceiver SoCs,” Proc. of IEEE Conf. on Microwaves, Communications, Antennas and Electronics Systems (COMCAS) Conf., pp. 1–4, Nov. 2009, Tel-Aviv, Israel. DOI: 10.1109/COMCAS.2009.5385949. [IEEE Xplore link]

[3] R. B. Staszewski, K. Waheed, S. Vemulapalli, P. Vallur, M. Entezari and O. Eliezer, “Elimination of spurious noise due to time-to-digital converter,” Proc. of Eighth IEEE Dallas Circuits and Systems Workshop: Energy Efficient Circuits and Systems (DCAS–09), pp. 67–70, Oct. 2009, Dallas, TX, USA. DOI: 10.1109/DCAS.2009.5505727. [IEEE Xplore link]

[4] K. Muhammad, C.-M. Hung, D. Leipold, T. Mayhugh, I. Elahi, I. Deng, C. Fernando, M.-C. Lee, T. Murphy, J. L. Wallberg, R. B. Staszewski, S. Larson, T. Jung, P. Cruise, V. Roussel, S. K. Vemulapalli, R. Staszewski, O. E. Eliezer, F. Feygin, K. Kunz and K. Maggio, “A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS,” Proc. of 2009 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO3A–4, pp. 197–200, June 2009, Boston, MA, USA. DOI: 10.1109/RFIC.2009.5135521. [IEEE Xplore link]

[5] I. Bashir, R. B. Staszewski, O. Eliezer, K. Waheed and P. T. Balsara, “An SoC with automatic bias optimization of an RF oscillator,” Proc. of 2009 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO3D–3, pp. 259–262, June 2009, Boston, MA, USA. DOI: 10.1109/RFIC.2009.5135535. [IEEE Xplore link]

[6] J. Tangudu, S. Gunturi, S. Jalan, J. Janardhanan, R. Ganesan, D. Sahu, K. Waheed, J. Wallberg and R. B. Staszewski, “Quantization noise improvement of Time to Digital converter (TDC) for ADPLL,” Proc. of 2009 IEEE Intl. Symp. on Circuits and Systems, pp. 1020–1023, May 2009, Taipei, Taiwan. DOI: 10.1109/ISCAS.2009.5117932. [IEEE Xplore link]

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2008

[1] J. Lopez, D. Y. Lie, R. B. Staszewski, D. Huang, C.-M. Hung and S. Swaminathan, “On the portability and performance of fully monolithic transformer structures for RF power amplfiers in standard CMOS process,” Proc. of Seventh IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS–08), pp. 103–106, Oct. 2008, Dallas, TX, USA. DOI: 10.1109/DCAS.2008.4695929. [IEEE Xplore link]

[2] I. L. Syllaios, P. T. Balsara and R. B. Staszewski, “Envelope and phase path recombination in ADPLL-based wideband polar transmitters,” Proc. of Seventh IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS–08), pp. 111–114, Oct. 2008, Dallas, TX, USA. DOI: 10.1109/DCAS.2008.4695931. [IEEE Xplore link]

[3] O. Eliezer, B. Staszewski, S. Bhatara, I. Bashir and P. T. Balsara, “Active mitigation of induced phase distortion in a GSM SoC,” Proc. of 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO1A–3, pp. 17–20, June 2008, Atlanta, GA, USA. DOI: 10.1109/RFIC.2008.4561376. [IEEE Xplore link]

[4] K. Waheed, R. B. Staszewski and S. Rezeq, “Curse of digital polar transmission: Precise delay alignment in amplitude and phase modulation paths,” Proc. of 2008 IEEE Intl. Symp. on Circuits and Systems, sec. 5.5, pp. 3142–3145, May 2008, Seattle, WA, USA. DOI: 10.1109/ISCAS.2008.4542124. [IEEE Xplore link]

[5] K. Waheed and R. B. Staszewski, “Mitigation of CMOS device variability in the transmitter amplitude path using Digital RF Processing,” Proc. of 2008 IEEE Intl. Symp. on Circuits and Systems, sec. 18.7, pp. 568–571, May 2008, Seattle, WA, USA. DOI: 10.1109/ISCAS.2008.4541481. [IEEE Xplore link]

[6] R. B. Staszewski, D. Leipold, O. Eliezer, M. Entezari, K. Muhammad, I. Bashir, C.-M. Hung, J. Wallberg, R. Staszewski, P. Cruise, S. Rezeq, S. Vemulapalli, K. Waheed, N. Barton, M.-C. Lee, C. Fernando, K. Maggio, T. Jung, I. Elahi, S. Larson, T. Murphy, G. Feygin, I. Deng, T. Mayhugh, Y.-C. Ho, K.-M. Low, C. Lin, J. Jaehnig, J. Kerr, J. Mehta, S. Glock, T. Almholt and S. Bhatara, “A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS,” Proc. of IEEE Solid-State Circuits Conf., sec. 10.5, pp. 208–209, 607, Feb. 2008, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2008.4523130. [IEEE Xplore link]

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2007

[1] R. B. Staszewski, “Modeling of an Electronic Noise and Media in a Magnetic Recording Read Channel Using VHDL,” Proc. of Sixth IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS–07), pp. 113–116, Nov. 2007, Dallas, TX, USA. DOI: 10.1109/DCAS.2007.4433197. [IEEE Xplore link]

[2] R. B. Staszewski, “Top-Down Simulation Methodology of a Mixed-Signal Read Channel Using Standard VHDL,” Proc. of Sixth IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS-07), pp. 109-112, Nov. 2007, Dallas, TX, USA. DOI: 10.1109/DCAS.2007.4433196. [IEEE Xplore link]

[3] E. Atalla, I. Bashir, P. Balsara, K. Kiasaleh and R. B. Staszewski, “A Practical Step Forward Toward Software-Defined Radio Transmitters,” Proc. of Sixth IEEE Dallas Circuits and Systems Workshop; SoC: Design, Application, Integration and Software (DCAS–07), pp. 63–66, Nov. 2007, Dallas, TX, USA. DOI: 10.1109/DCAS.2007.4433217. [IEEE Xplore link]

[4] I. L. Syllaios, P. T. Balsara and R. B. Staszewski, “Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications,” Proc. of 2007 IEEE Custom Integrated Circuits Conf., sec. 27.6, pp. 861–864, Sept. 2007, San Jose, CA, USA. DOI: 10.1109/CICC.2007.4405864. [IEEE Xplore link]

[5] I. L. Syllaios, P. T. Balsara and R. B. Staszewski, “On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios,” Proc. of 18th IEEE Annual International Symposium on Personal Indoor and Mobile Radio Communications (PIMRC 2007)., no. 1106, pp. 1–6, Sept. 2007, Athens, Greece. DOI: 10.1109/PIMRC.2007.4394091. [IEEE Xplore link]

[6] O. Eliezer, I. Bashir, R. B. Staszewski and P. T. Balsara, “Built-in Self Testing of a DRP-Based GSM Transmitter,” Proc. of 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO4D-2, pp. 339–342, June 2007, Honolulu, HI, USA. DOI: 10.1109/RFIC.2007.380896. [IEEE Xplore link]

[7] S. Akhtar, P. Litmanen, M. Ipek, J. (H.-C.) Lin , S. Pennisi, F.-J. Huang and R. B. Staszewski, “Analog Path for Triple Band WCDMA Polar Modulated Transmitter in 90nm CMOS,” Proc. of 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO3A-2, pp. 185–188, June 2007, Honolulu, HI, USA. DOI: 10.1109/RFIC.2007.380861. [IEEE Xplore link]

[8] R. B. Staszewski, K. Muhammad and O. Eliezer, “Digital RF Processor (DRP™) for Mobile Phones,” Proc. of 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO3A–1, pp. 181–184, June 2007, Honolulu, HI, USA. DOI: 10.1109/RFIC.2007.380860. [IEEE Xplore link]

[9] K. Waheed, R. B. Staszewski and J. Wallberg, “Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation,” Proc. of 2007 IEEE Intl. Symp. on Circuits and Systems, sec. 5.5, pp. 3291–3294, May 2007, New Orleans, LA, USA. DOI: 10.1109/ISCAS.2007.378214. [IEEE Xplore link]

[10] K. Waheed and R. B. Staszewski, “Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS,” Proc. of 2007 IEEE Intl. Symp. on Circuits and Systems, sec. 19.3, pp. 1253–1256, May 2007, New Orleans, LA, USA. DOI: 10.1109/ISCAS.2007.378338. [IEEE Xplore link]

[11] R. Staszewski, T. Jung, R. B. Staszewski, D. Leipold and T. Murphy, “Software Aspects of the Digital RF Processor (DRP™),” Proc. of IEEE International Conf. on IC Design and Technology (ICICDT) pp. 1–5, May/June. 2007, Austin, TX, USA. DOI: 10.1109/ICICDT.2007.4299560. [IEEE Xplore link]

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2006

[1] W. Krenik and R. B. Staszewski, “Fully-integrated CMOS RF transceivers,” Proc. of 2006 IEEE Asia-Pacific Microwave Conf. (APMC), sec. FR4A–5, pp. 1795–1800, Dec. 2006, Yokohama, Japan. DOI: 10.1109/APMC.2006.4429758. [IEEE Xplore link]

[2] R. B. Staszewski, J. Wallberg and P. T. Balsara, “All-Digital PLL with Variable Loop Type Characteristics,” Proc. of Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS–06), pp. 115–118, Oct. 2006, Dallas, TX, USA. DOI: 10.1109/DCAS.2006.321047. [IEEE Xplore link]

[3] I. Bashir, R. B. Staszewski and O. Eliezer, “Tuning Word Retiming of a Digitally-Controlled Oscillator Using RF Built-In Self Test,” Proc. of Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS–06), pp. 103–106, Oct. 2006, Dallas, TX, USA. DOI: 10.1109/DCAS.2006.321044. [IEEE Xplore link]

[4] S. D. Vamvakos, R. B. Staszewski, M. Sheba and K. Waheed, “Noise Analysis of Time-to-Digital Converter in All-Digital PLLs,” Proc. of Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS–06), pp. 87–90, Oct. 2006, Dallas, TX, USA. DOI:10.1109/DCAS.2006.321040. [IEEE Xplore link]

[5] O. Eliezer, O. Friedman and R. B. Staszewski, “A built-in tester for modulation noise in a wireless transmitter,” Proc. of Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS–06), pp. 59–62, Oct. 2006, Dallas, TX, USA. DOI: 10.1109/DCAS.2006.321033. [IEEE Xplore link]

[6] R. B. Staszewski, K. Muhammad and D. Leipold, “Digital RF processing techniques for SoC radios (invited),” Proc. of 2006 IEEE Custom Integrated Circuits Conf., sec. 27.1, pp. 789–796, Sept. 2006, San Jose, CA, USA. DOI: 10.1109/CICC.2006.320998. [IEEE Xplore link]

[7] R. B. Staszewski, K. Muhammad and D. Leipold, “Digital Signal Processing for RF at 45-nm CMOS and Beyond,” Proc. of 2006 IEEE Custom Integrated Circuits Conf., sec. 13.1, pp. 517–522, Sept. 2006, San Jose, CA, USA. DOI: 10.1109/CICC.2006.320904. [IEEE Xplore link]

[8] S. Akhtar, M. Ipek, J. (H.-C.) Lin , R. B. Staszewski and P. Litmanen, “Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS,” Proc. of 2006 IEEE Custom Integrated Circuits Conf., sec. 7.4, pp. 129–132, Sept. 2006, San Jose, CA, USA. DOI: 10.1109/CICC.2006.320849. [IEEE Xplore link]

[9] R. Staszewski, T. Jung, R. B. Staszewski, K. Muhammad, D. Leipold, T. Murphy, S. Sabin, J. Wallberg, S. Larson, M. Entezari, J. Fresquez, S. Dondershine and S. Syed, “Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS,” Proc. of 2006 IEEE Custom Integrated Circuits Conf., sec. 6.1, pp. 81–84, Sept. 2006, San Jose, CA, USA. DOI: 10.1109/CICC.2006.320981. [IEEE Xplore link]

[10] B. Staszewski and C.-M. Hung, “Frequency synthesis in a digital RF processor (DRP™) for mobile phones,” Proc. of The Sixth Annual Emerging Information Technology Conf. (EITC 2006), sec. T2, Aug. 2006, Dallas, TX, USA. [EITC link]

[11] R. B. Staszewski, P. Cruise and D. Leipold, “Crystal Drift Compensation in a Mobile Phone,” Proc. of 2006 IET Irish Signals and Systems Conf., pp. 241–245, June 2006, Dublin, Ireland. Print ISBN: 0-86341-665-9. [IEEE Xplore link]

[12] K. Muhammad, T. Murphy and R. B. Staszewski, “Verification of RF SoCs: RF, analog, baseband and software,” Proc. of 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RTU1C–1, pp. 407–410, June 2006, San Francisco, CA, USA. DOI: 10.1109/RFIC.2006.1651166. [IEEE Xplore link]

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2005

[1] R. B. Staszewski, K. Muhammad and D. Leipold, “Digital RF processor (DRP™) for cellular phones,” Proc. of IEEE 23rd Norchip Conf., pp. 1–4, Nov. 2005, Oulu, Finland. DOI: 10.1109/NORCHP.2005.1596975. [IEEE Xplore link]

[2] R. B. Staszewski, K. Muhammad and D. Leipold, “Digital RF processor (DRP™) for cellular phones,” Proc. of IEEE International Conf. on Computer Aided Design (ICCAD), pp. 122–129, Nov. 2005, San Jose, CA, USA. DOI: 10.1109/ICCAD.2005.1560051. [IEEE Xplore link]

[3] R. B. Staszewski, G. Shriki and P. T. Balsara, “All-Digital PLL with Ultra Fast Acquisition” Proc. of IEEE Asian Solid-State Circuits Conf. (ASSCC), sec. 11–7, pp. 289–292, Nov. 2005, Taipei, Taiwan. DOI: 10.1109/ASSCC.2005.251722. [IEEE Xplore link]

[4] R. B. Staszewski, C.-M. Hung and Y.-C. Ho, “RF amplitude control in an all-digital PLL based transmitter,” Proc. of International SoC Design Conference (ISOCC), sec. 12, pp. 203–206, Oct. 2005, Seoul, Korea.

[5] Y.-C. Ho, C.-M. Hung, K. Muhammad, C. Fernando, P. Cruise, R. B. Staszewski, D. Leipold and K. Maggio, “A 1.8dB NF receiver front-end for GSM/GPRS in a 90nm digital CMOS,” Proc. of International SoC Design Conference (ISOCC), ses. 12, pp. 211–214, Oct. 2005, Seoul, Korea.

[6] R. B. Staszewski and R. Staszewski, “Interpolative pulse-shape filtering for a GSM/Bluetooth transmitter,” Proc. of 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS–05), pp. 191–194, Oct. 2005, Dallas, TX, USA. DOI: 10.1109/DCAS.2005.1611168. [IEEE Xplore link]

[7] V. K. Parikh, G. Feygin, P. T. Balsara, S. Rezeq,R. B. Staszewski, S. Vemulapalli and O. Eliezer, “Implementation of a high speed digital band-pass sigma-delta modulator for a wireless transmitter,” Proc. of 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS-05), pp. 207–210, Oct. 2005, Dallas, TX, USA. DOI: 10.1109/DCAS.2005.1611172. [IEEE Xplore link]

[8] Y.-C. Ho, K. Muhammad, M.-C. Lee, C.-M. Hung, J. Wallberg, C. Fernando, P. Cruise, R. B. Staszewski, D. Leipold and K. Maggio, “A GSM/GPRS receiver front-end with discrete-time filters in a 90 nm digital CMOS,” Proc. of 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS-05), pp. 199–202, Oct. 2005, Dallas, TX, USA. DOI: 10.1109/DCAS.2005.1611170. [IEEE Xplore link]

[9] I. Bashir, R. B. Staszewski, O. Eliezer and E. de-Obaldia, “Built-in self testing (BIST) of RF performance in a system-on-chip (SoC),” Proc. of 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS–05), pp. 215–218, Oct. 2005, Dallas, TX, USA. DOI: 10.1109/DCAS.2005.1611174. [IEEE Xplore link]

[10] K. Waheed and R. B. Staszewski, “Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator,” Proc. of 2005 IEEE Custom Integrated Circuits Conf., sec. 18–3,pp. 605–608, Sept. 2005, San Jose, CA, USA. DOI: 10.1109/CICC.2005.1568740. [IEEE Xplore link]

[11] K. Muhammad, Y.-C. Ho, T. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. B. Staszewski, R. Staszewski and K. Maggio, “A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process,” Proc. of 2005 IEEE Custom Integrated Circuits Conf., sec. 28–5, pp. 809–812, Sept. 2005, San Jose, CA, USA. DOI: 10.1109/CICC.2005.1568792. [IEEE Xplore link]

[12] K. Waheed and R. B. Staszewski, “Time-domain behavioral modeling of a multigigahertz digital RF oscillator using VHDL,” Proc. of IEEE Midwest Symp. on Circuits and Systems, session C3L-B, pp. 1669-1672, Aug. 2005, Cincinnati, OH, USA. DOI: 10.1109/MWSCAS.2005.1594439. [IEEE Xplore link]

[13] K. Waheed and R. B. Staszewski, “Harmonic characterization of mismatches in deep sub-micron varactors for a digitally controlled RF oscillator,” Proc. of IEEE Midwest Symp. on Circuits and Systems, session B3L–G, pp. 951–954, Aug. 2005, Cincinnati, OH, USA. DOI: 10.1109/MWSCAS.2005.1594260. [IEEE Xplore link]

[14] R. B. Staszewski, R. Staszewski and P. T. Balsara, “VHDL simulation and modeling of an all-digital RF transmitter,” Proc. of IEEE Fifth Intl. Workshop on SoC for Real-Time Applications, pp. 233–238, July 2005, Banff, Canada. DOI: 10.1109/IWSOC.2005.112. [IEEE Xplore link]

[15] R. B. Staszewski, S. Rezeq, C.-M. Hung, P. Cruise and J. Wallberg, “Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion,” Proc. of IEEE Fifth Intl. Workshop on SoC for Real-Time Applications, pp. 154–159, July 2005, Banff, Canada. DOI: 10.1109/IWSOC.2005.97. [IEEE Xplore link]

[16] R. B. Staszewski, K. Muhammad and D. Leipold, “Digital RF processing techniques for SoC radios (invited),” Proc. of IEEE Fifth Intl. Workshop on SoC for Real-Time Applications, pp. 217–222, July 2005, Banff, Canada. DOI: 10.1109/IWSOC.2005.54. [IEEE Xplore link]

[17] C.-M. Hung, N. Barton, R. B. Staszewski, M.-C. Lee and D. Leipold, “A first RF digitally-controlled oscillator for SAW-less TX in cellular systems,” Proc. of 2005 IEEE Symp. on VLSI Circuits, sec. 25.3, pp. 402–405, June 2005, Kyoto, Japan. DOI: 10.1109/VLSIC.2005.1469414. [IEEE Xplore link]

[18] R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg and P. T. Balsara, “Time-to-digital converter for RF frequency synthesis in 90 nm CMOS,” Proc. of 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RTU3B–4, pp. 473–476, June 2005, Long Beach, CA, USA. DOI: 10.1109/RFIC.2005.1489847. [IEEE Xplore link]

[19] R. B. Staszewski, C.-M. Hung, N. Barton, M.-C. Lee and D. Leipold, “A first RF digitally-controlled oscillator for mobile phones,” Proc. of 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO2B–1, pp. 119–122, June 2005, Long Beach, CA, USA. DOI: 10.1109/RFIC.2005.1489605. [IEEE Xplore link]

[20] P. Cruise, C.-M. Hung, R. B. Staszewski, O. Eliezer, S. Rezeq, D. Leipold and K. Maggio, “A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS,” Proc. of 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. RMO1A–4, pp. 21–24, June 2005, Long Beach, CA, USA. DOI: 10.1109/RFIC.2005.1489176. [IEEE Xplore link]

[21] R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad and D. Leipold, “ All-digital PLL and GSM/EDGE transmitter in 90nm CMOS,” Proc. of IEEE Solid-State Circuits Conf., sec. 17.5, pp. 316–317, 600, Feb. 2005, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2005.1493996. [IEEE Xplore link]

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2004

[1] J. Koh, K. Muhammad, B. Staszewski, G. Gomez and B. Horoun, “ A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process,” Proc. of 2004 IEEE Custom Integrated Circuits Conf., sec. 25–6, pp. 535–538, Oct. 2004, Orlando, FL, USA. DOI: 10.1109/CICC.2004.1358877. [IEEE Xplore link]

[2] R. B. Staszewski, J. Wallberg and J. Koh, “High-speed digital circuits for a 2.4 GHz all-digital RF frequency synthesizer in 130 nm CMOS,” Proc. of 2004 IEEE Dallas CAS Workshop: Implementation of High Performance Circuits, pp. 167–170, Sept. 2004, Dallas, TX, USA. DOI: 10.1109/DCAS.2004.1360452. [IEEE Xplore link]

[3] R. B. Staszewski, R. Staszewski, J. Wallberg, T. Jung, C.-M. Hung, D. Leipold, K. Maggio and P. T. Balsara, “DSP-coupled 2.4 GHz RF transmitter in 130 nm CMOS,” Proc. of 2004 IEEE Dallas CAS Workshop: Implementation of High Performance Circuits, pp. 163–166, Sept. 2004, Dallas, TX, USA. DOI: 10.1109/DCAS.2004.1360451. [IEEE Xplore link]

[4] R. B. Staszewski, D. Leipold, C.-M. Hung and P. T. Balsara, “TDC-based frequency synthesizer for wireless applications,” Proc. of 2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. MO2D–3, pp. 215–218, June 2004, Fort Worth, TX, USA. DOI: 10.1109/RFIC.2004.1320575. [IEEE Xplore link]

[5] K. Muhammad, R. B. Staszewski and C.-M. Hung, “Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver,” Proc. of 2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. TU3C–2, pp. 405–408, June 2004, Fort Worth, TX, USA. DOI: 10.1109/RFIC.2004.1320636. [IEEE Xplore link]

[6] R. B. Staszewski, C. Fernando and P. T. Balsara, “Event-driven simulation and modeling of an RF oscillator,” Proc. of 2004 IEEE Intl. Symp. on Circuits and Systems, sec. NLCS–L6.3, pp. IV–641–IV–644, May 2004, Vancouver, Canada. DOI: 10.1109/ISCAS.2004.1329085. [IEEE Xplore link]

[7] K. Muhammad and R. B. Staszewski, “Direct RF sampling mixer with recursive filtering in charge domain,” Proc. of 2004 IEEE Intl. Symp. on Circuits and Systems, sec. ASP–L29.5, pp. I–577–I–580, May 2004, Vancouver, Canada. DOI: 10.1109/ISCAS.2004.1328260 [IEEE Xplore link]

[8] B. Staszewski, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold and P. Balsara, “All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13µm CMOS,” Proc. of IEEE Solid-State Circuits Conf., sec. 15.3, pp. 272–273, 527, Feb. 2004, San Francisco, CA, USA. DOI:10.1109/ISSCC.2004.1332699. [IEEE Xplore link]

[9] K. Muhammad, D. Leipold,B. Staszewski, Y.-C. Ho, C.-M. Hung, K. Maggio, C. Fernando, T. Jung, J. Wallberg, J.-S. Koh, S. John, I. Deng, O. Moreira, R. Staszewski, R. Katz and O. Friedman, “A discrete-time Bluetooth receiver in a 0.13µm digital CMOS process,” Proc. of IEEE Solid-State Circuits Conf., sec. 15.1, pp. 268–269, 527, Feb. 2004, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2004.1332697. [IEEE Xplore link]

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2003

[1] R. B. Staszewski, D. Leipold, J. Wallberg and P. T. Balsara, “Just-in-time gain estimation of an RF digitally-controlled oscillator,” Proc. of 2003 IEEE Custom Integrated Circuits Conf., sec. 25–8, pp. 571–574, Sept. 2003, San Jose, CA, USA. DOI: 10.1109/CICC.2003.1249463. [IEEE Xplore link]

[2] R. B. Staszewski, D. Leipold, C.-M. Hung and P. T. Balsara, “A first digitally-controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications,” Proc. of 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., sec. MO4B–2, pp. 81–84, June 2003, Philadelphia, PA, USA. DOI: 10.1109/RFIC.2003.1213898. [IEEE Xplore link]

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2001

[1] K. Muhammad,R. B. Staszewski and P. T. Balsara, “Challenges in integrated CMOS transceivers for short distance wireless,” Proc. of 11th Great Lakes Symposium on VLSI, pp. 45–50, 22–23 Mar. 2001, (invited paper), Chicago, IL, USA. DOI: 10.1145/368122.368747. [ACM link]

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2000

[1] R. B. Staszewski, K. Muhammad and P. Balsara, “A constrained asymmetry LMS algorithm for PRML disk drive read channels,” Proc. of the 34th Asilomar Conf. On Signals, Systems and Computers, sec. MP6a.3, pp. 433–437, Nov. 2000, Pacific Grove, CA, USA. DOI: 10.1109/ACSSC.2000.910992. [IEEE Xplore link]

[2] K. Muhammad, R. B. Staszewski and P. T. Balsara, “Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels,” Proc. of IEEE International Symposium on Low Power Electronics and Design, sec. 9.2, pp. 262–267, July 2000, Rapallo, Italy. DOI: 10.1145/344166.344623. [IEEE Xplore link]

[3] R. B. Staszewski, K. Muhammad and P. Balsara, “A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels,” Proc. of IEEE Solid-State Circuits Conf., sec. MP4.7, pp. 80–81, Feb. 2000, San Francisco, CA, USA. DOI: 10.1109/ISSCC.2000.839700. [IEEE Xplore link]

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1999

[1] R. B. Staszewski and S. Kiriaki, “Top-down simulation methodology of a 500 MHz mixed-signal magnetic recording read channel using standard VHDL,” Proc. of Behavioral Modeling and Simulation Conf., sec. 3.2, Oct. 1999, Orlando, FL, USA. [BMAS link]

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1997

[1] G. Feygin, B. Staszewski and S. Kiriaki, “Area and power efficient implementation of LMS adaptive equalization for an analog PRML read channel,” Proc. of EE-Times Analog and Mixed-Signal Applications Conf., sec. 2C, pp. 229–234, July 1997, San Jose, CA, USA.

[2] S. Kiriaki, T. L. Viswanathan, G. Feygin, B. Staszewski, R. Pierson, B. Krenik, M. de Wit and K. Nagaraj, “A 160-MHz analog equalizer for magnetic disk read channels,” Proc. of IEEE Solid-State Circuits Conf., sec. SA19.5, pp. 322–323, 479, Feb. 1997, San Francisco, CA, USA. DOI: 10.1109/ISSCC.1997.585402. [IEEE Xplore link]

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