Published US Patents: Accessed from http://patft.uspto.gov/

---

2015

PHASE-LOCKED LOOP CIRCUIT

FREQUENCY MODULATOR HAVING DIGITALLY-CONTROLLED OSCILLATOR WITH MODULATION TUNING AND PHASE-LOCKED LOOP

DIGITAL PHASE LOCKED LOOP

OSCILLATOR BUFFER AND METHOD FOR CALIBRATING THE SAM

---

2014

WIDEBAND FM DEMODULATION BY INJECTION-LOCKED DIVISION OF FREQUENCY DEVIATION

OSCILLATOR

PHASE LOCKED LOOP (PLL) WITH MULTI-PHASE TIME-TO-DIGITAL CONVERTER (TDC)

RADIO FREQUENCY RECIEVER

HIGH-IF SUPERHETERODYNE RECEIVER INCORPORATING HIGH-Q COMPLEX BAND PASS FILTER

DIGITALLY-CONTROLLED POWER AMPLIFIER WITH BANDPASS FILTERING/TRANSIENT WAVEFORM CONTROL AND RELATED DIGITALLY-CONTROLLED POWER AMPLIFIER CELL

HIGH RESOLUTION MILLIMETER WAVE DIGITALLY CONTROLLED OSCILLATOR WITH RECONFIGURABLE DISTRIBUTED METAL CAPACITOR PASSIVE RESONATORS

DIGITAL PHASE LOCKED LOOP

---

2013

TRANSMITTER

FREQUENCY MODULATOR HAVING DIGITALLY-CONTROLLED OSCILLATOR ARRANGED FOR RECEIVING MODULATION TUNING WORD AND PHASE-LOCKED LOOP TUNING WORD AND/OR RECEIVING FRACTIONAL TUNING WORD OBTAINED THROUGH ASYNCHRONOUS SAMPLING AND INTEGER TUNING WORD

CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF

METHOD AND APPARATUS OF ESTIMATING/CALIBRATING TDC GAIN

TRANSMITTER AND FREQUENCY DEVIATION REDUCTION METHOD THEREOF

POLAR TRANSMITTER HAVING DIGITAL PROCESSING BLOCK USED FOR ADJUSTING FREQUENCY MODULATING SIGNAL FOR FREQUENCY DEVIATION OF FREQUENCY MODULATED CLOCK AND RELATED METHOD THEREOF

METHOD AND APPARATUS OF ESTIMATING/CALIBRATING TDC MISMATCH

POLAR TRANSMITTER HAVING FREQUENCY MODULATING PATH WITH INTERPOLATION IN COMPENSATING FEED INPUT AND RELATED METHOD THEREOF

OSCILLATOR CIRCUIT AND METHOD FOR GENERATING AN OSCILLATION

DIGITALLY-CONTROLLED POWER AMPLIFIER WITH BANDPASS FILTERING/TRANSIENT WAVEFORM CONTROL AND RELATED DIGITALLY-CONTROLLED POWER AMPLIFIER CELL

TRANSMITTER EMPLOYING PULLING MITIGATION MECHANISM AND RELATED METHOD THEREOF

MULTI-STAGE DIGITALLY-CONTROLLED POWER AMPLIFIER

DIGITAL PHASE LOCKED LOOP

TIME-TO-DIGITAL SYSTEM AND ASSOCIATED FREQUENCY SYNTHESIZER

FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD, Part1

FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD, Part2

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

TRANSMITTER EMPLOYING PULLING MITIGATION MECHANISM AND RELATED METHOD THEREOF

DIGITALLY-CONTROLLED POWER AMPLIFIER WITH BANDPASS FILTERING/TRANSIENT WAVEFORM CONTROL AND RELATED DIGITALLY-CONTROLLED POWER AMPLIFIER CELL

---

2012

LINEARIZATION OF A TRANSMIT AMPLIFIER

PREDISTORTION CALIBRATION AND BUILT IN SELF TESTING OF A RADIO FREQUENCY POWER AMPLIFIER USING SUBHARMONIC MIXING

MINIMIZATION OF RMS PHASE ERROR IN A PHASE LOCKED LOOP BY DITHERING OF A FREQUENCY REFERENCE

DIGITAL AMPLITUDE MODULATION

CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC..

APPARATUS AND METHOD FOR CALIBRATING TIMING MISMATCH OF EDGE ROTATOR OPERATING ON MULTIPLE PHASES OF OSCILLATOR

---

2011

ALL-DIGITAL FREQUENCY SYNTHESIS WITH DCO GAIN CALCULATION

DIGITAL AMPLITUDE MODULATION

DIGITAL PHASE LOCKED LOOP WITH DITHERING

DIGITAL POWER AMPLIFIER WITH I1Q COMBINATION

INTEGRATED CIRCUIT, COMMUNICATION UNIT AND METHOD FOR IMPROVED AMPLITUDE RESOLUTION OF AN RF-DAC

---

2010

DIGITAL PHASE LOCKED LOOP WITH DITHERING

MITIGATION OF RF OSCILLATOR PULLING THROUGH ADJUSTABLE PHASE SHIFTING

PREDISTORTION MECHANISM FOR COMPENSATION OF TRANSISTOR SIZE MISMATCH IN A DIGITAL POWER AMPLIFIER

UPSAMPLING/INTERPOLATION AND TIME ALIGNMENT MECHANISM UTILIZING INJECTION OF HIGH FREQUENCY NOISE

SIMULTANEOUS MULTIPLE SIGNAL RECEPTION AND TRANSMISSION USING FREQUENCY MULTIPLEXING AND SHARED PROCESSING

---

2009

COMPUTATION SPREADING UTILIZING DITHERING FOR SPUR REDUCTION IN A DIGITAL PHASE LOCK LOOP

DIRECT RADIO FREQUENCY (RF) SAMPLING WITH RECURSIVE FILTERING METHOD

TRANSMITTER PLL WITH BANDWIDTH ON DEMAND

BANDWIDTH REDUCTION MECHANISM FOR POLAR MODULATION

SYSTEM AND METHOD FOR IMPEDANCE MISMATCH COMPENSATION IN DIGITAL COMMUNICATIONS SYSTEMS

POWER AMPLIFIER

DIGITAl POWER AMPLIFIER WITH 1/Q COMBINATION

---

2008

LOW POWER ALL DIGITAL PLL ARCHITECTURE

DIGITAL PHASE LOCKED LOOP WITH INTEGER CHANNEL MITIGATION

SECOND-ORDER POLYNOMIAL, INTERPOLATION-BASED, SAMPLING RATE CONVERTER AND METHOD AND TRANSMITTERS EMPLOYING THE SAME

VARIABLE DELAY OSCILLATOR BUFFER

PHASE ALIGNMENT MECHANISM FOR MINIMIZING THE IMPACT OF INTEGER-CHANNEL INTERFERENCE IN A PHASE LOCKED LOOP

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

LOCAL OSCILLATOR WITH NON-HARMONIC RATIO BETWEEN OSCILLATOR AND RF FREQUENCIES USING XOR OPERATION

ON-CHIP RECEIVER SENSITIVITY TEST MECHANISM

---

2007

DELAY ALIGNMENT IN A CLOSED LOOP TWO-POINT MODULATION ALL DIGITAL PHASE LOCKED LOOP

LINEARIZATION OF A TRANSMIT AMPLIFIER

GAIN CALIBRATION OF A DIGITAL CONTROLLED OSCILLATOR

SAMPLING MIXER WITH ASYNCHRONOUS CLOCK AND SIGNAL DOMAINS

---

2006

REMOVING CLOSE-IN INTERFERERS THROUGH A FEEDBACK LOOP

MULTI-FUNCTION DIGITAL DEVICE AS A HUMAN-INPUT-DEVICE FOR A COMPUTER

---

2005

IMAGE REJECT FILTERING IN A DIRECT SAMPLING MIXER

APPARATUS FOR AND METHOD OF NOISE SUPPRESSION AND DITHERING TO IMPROVE RESOLUTION QUALITY IN A DIGITAL RF PROCESSOR

ACTIVE REMOVAL OF ALIASING FREQUENCIES IN A DECIMATING STRUCTURE BY CHANGING A DECIMATION RATIO IN TIME AND SPACE

HIGH-SPEED MASH SIGMA-DELTA MODULATOR ARCHITECTURE AND METHOD OF OPERATION THEREOF

METHOD AND APPARATUS FOR CRYSTAL DRIFT COMPENSATION

METHOD OF RATE CONVERSION TOGETHER WITH I-Q MISMATCH CORRECTION AND SAMPLER PHASE ADJUSTMENT IN DIRECT SAMPLING BASED DOWN-CONVERSION

SAMPLING MIXER WITH ASYNCHRONOUS CLOCK AND SIGNAL DOMAINS

---

2004

RADIO FREQUENCY BUILT-IN SELF TEST FOR QUALITY MONITORING OF LOCAL OSCILLATOR AND TRANSMITTER

METHOD AND ARCHITECTURE FOR CONTROLLING ASYMMETRY OF AN LMS ADAPTATION ALGORITHM THAT CONTROLS FIR FILTER COEFFICIENTS

2003

FINE-GRAINED GEAR-SHIFTING OF A DIGITAL PHASE-LOCKED LOOP (PLL)

2002

FINITE-IMPULSE-RESPONSE (FIR) FILTER EMPLOYING A PARALLELARCHITECTURE

METHOD AND APPARATUS FOR ASYNCHRONOUS CLOCK RETIMING

DIGITAL PHASE LOCKED LOOP

1998

EUROPEAN PATENT APPLICATION: SYNC DETECT CIRCUIT